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00032 #ifndef _ATH_AH_H_
00033 #define _ATH_AH_H_
00034
00035 #include "compat.h"
00036
00037 typedef void* HAL_SOFTC;
00038
00039 typedef struct {
00040 u_int32_t ns_avgbrssi;
00041 u_int32_t ns_avgrssi;
00042 u_int32_t ns_avgtxrssi;
00043 } HAL_NODE_STATS;
00044
00045
00046 #define IEEE80211_ADDR_LEN 6
00047 typedef int HAL_BUS_TAG;
00048 typedef void* HAL_BUS_HANDLE;
00049 typedef u_int32_t HAL_BUS_ADDR;
00050
00051
00052
00053
00054
00055 enum ar5k_version {
00056 AR5K_AR5210 = 0,
00057 AR5K_AR5211 = 1,
00058 AR5K_AR5212 = 2,
00059 };
00060
00061 enum ar5k_radio {
00062 AR5K_AR5110 = 0,
00063 AR5K_AR5111 = 1,
00064 AR5K_AR5112 = 2,
00065 };
00066
00067
00068
00069
00070
00071 typedef enum {
00072 AH_FALSE = 0,
00073 AH_TRUE,
00074 } HAL_BOOL;
00075
00076 typedef enum {
00077 HAL_MODE_11A = 0x001,
00078 HAL_MODE_TURBO = 0x002,
00079 HAL_MODE_11B = 0x004,
00080 HAL_MODE_PUREG = 0x008,
00081 HAL_MODE_11G = 0x008,
00082 HAL_MODE_108G = 0x020,
00083 HAL_MODE_XR = 0x040,
00084 HAL_MODE_ALL = 0xfff
00085 } HAL_MODE;
00086
00087 typedef enum {
00088 HAL_ANT_VARIABLE = 0,
00089 HAL_ANT_FIXED_A = 1,
00090 HAL_ANT_FIXED_B = 2,
00091 HAL_ANT_MAX = 3,
00092 } HAL_ANT_SETTING;
00093
00094 typedef enum {
00095 HAL_M_STA = 1,
00096 HAL_M_IBSS = 0,
00097 HAL_M_HOSTAP = 6,
00098 HAL_M_MONITOR = 8,
00099 } HAL_OPMODE;
00100
00101 typedef int HAL_STATUS;
00102
00103 #define HAL_OK 0
00104 #define HAL_EINVAL 1
00105 #define HAL_EINPROGRESS EINPROGRESS
00106
00107
00108
00109
00110
00111 typedef enum {
00112 HAL_TX_QUEUE_INACTIVE = 0,
00113 HAL_TX_QUEUE_DATA,
00114 HAL_TX_QUEUE_BEACON,
00115 HAL_TX_QUEUE_CAB,
00116 HAL_TX_QUEUE_PSPOLL,
00117 } HAL_TX_QUEUE;
00118
00119 #define HAL_NUM_TX_QUEUES 10
00120
00121 typedef enum {
00122 HAL_TX_QUEUE_ID_DATA_MIN = 0,
00123 HAL_TX_QUEUE_ID_DATA_MAX = 6,
00124 HAL_TX_QUEUE_ID_PSPOLL = 7,
00125 HAL_TX_QUEUE_ID_BEACON = 8,
00126 HAL_TX_QUEUE_ID_CAB = 9,
00127 } HAL_TX_QUEUE_ID;
00128
00129 typedef enum {
00130 HAL_WME_AC_BK = 0,
00131 HAL_WME_AC_BE = 1,
00132 HAL_WME_AC_VI = 2,
00133 HAL_WME_AC_VO = 3,
00134 HAL_WME_UPSD = 4,
00135 } HAL_TX_QUEUE_SUBTYPE;
00136
00137 #define TXQ_FLAG_TXINT_ENABLE 0x0001
00138 #define TXQ_FLAG_TXDESCINT_ENABLE 0x0002
00139 #define TXQ_FLAG_BACKOFF_DISABLE 0x0004
00140 #define TXQ_FLAG_COMPRESSION_ENABLE 0x0008
00141 #define TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0010
00142 #define TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0020
00143 #define TXQ_FLAG_POST_FR_BKOFF_DIS 0x0040
00144 #define TXQ_FLAG_TXEOLINT_ENABLE 0x0080
00145 typedef struct {
00146 u_int32_t tqi_ver;
00147 HAL_TX_QUEUE tqi_type;
00148 HAL_TX_QUEUE_SUBTYPE tqi_subtype;
00149 u_int16_t tqi_qflags;
00150 u_int32_t tqi_priority;
00151 u_int32_t tqi_aifs;
00152 int32_t tqi_cwmin;
00153 int32_t tqi_cwmax;
00154 u_int32_t tqi_cbrPeriod;
00155 u_int32_t tqi_cbrOverflowLimit;
00156 u_int32_t tqi_burstTime;
00157 u_int32_t tqi_readyTime;
00158 } HAL_TXQ_INFO;
00159
00160 typedef enum {
00161 HAL_PKT_TYPE_NORMAL = 0,
00162 HAL_PKT_TYPE_ATIM = 1,
00163 HAL_PKT_TYPE_PSPOLL = 2,
00164 HAL_PKT_TYPE_BEACON = 3,
00165 HAL_PKT_TYPE_PROBE_RESP = 4,
00166 HAL_PKT_TYPE_PIFS = 5,
00167 } HAL_PKT_TYPE;
00168
00169
00170
00171
00172
00173 #define AR5K_CCK_SIFS_TIME 10
00174 #define AR5K_CCK_PREAMBLE_BITS 144
00175 #define AR5K_CCK_PLCP_BITS 48
00176 #define AR5K_CCK_NUM_BITS(_frmlen) (_frmlen << 3)
00177 #define AR5K_CCK_PHY_TIME(_sp) (_sp ? \
00178 ((AR5K_CCK_PREAMBLE_BITS + AR5K_CCK_PLCP_BITS) >> 1) : \
00179 (AR5K_CCK_PREAMBLE_BITS + AR5K_CCK_PLCP_BITS))
00180 #define AR5K_CCK_TX_TIME(_kbps, _frmlen, _sp) \
00181 AR5K_CCK_PHY_TIME(_sp) + \
00182 ((AR5K_CCK_NUM_BITS(_frmlen) * 1000) / _kbps) + \
00183 AR5K_CCK_SIFS_TIME
00184
00185 #define AR5K_OFDM_SIFS_TIME 16
00186 #define AR5K_OFDM_PREAMBLE_TIME 20
00187 #define AR5K_OFDM_PLCP_BITS 22
00188 #define AR5K_OFDM_SYMBOL_TIME 4
00189 #define AR5K_OFDM_NUM_BITS(_frmlen) (AR5K_OFDM_PLCP_BITS + (_frmlen << 3))
00190 #define AR5K_OFDM_NUM_BITS_PER_SYM(_kbps) ((_kbps * \
00191 AR5K_OFDM_SYMBOL_TIME) / 1000)
00192 #define AR5K_OFDM_NUM_BITS(_frmlen) (AR5K_OFDM_PLCP_BITS + (_frmlen << 3))
00193 #define AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen) \
00194 howmany(AR5K_OFDM_NUM_BITS(_frmlen), AR5K_OFDM_NUM_BITS_PER_SYM(_kbps))
00195 #define AR5K_OFDM_TX_TIME(_kbps, _frmlen) \
00196 AR5K_OFDM_PREAMBLE_TIME + AR5K_OFDM_SIFS_TIME + \
00197 (AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_OFDM_SYMBOL_TIME)
00198
00199 #define AR5K_TURBO_SIFS_TIME 8
00200 #define AR5K_TURBO_PREAMBLE_TIME 14
00201 #define AR5K_TURBO_PLCP_BITS 22
00202 #define AR5K_TURBO_SYMBOL_TIME 4
00203 #define AR5K_TURBO_NUM_BITS(_frmlen) (AR5K_TURBO_PLCP_BITS + (_frmlen << 3))
00204 #define AR5K_TURBO_NUM_BITS_PER_SYM(_kbps) (((_kbps << 1) * \
00205 AR5K_TURBO_SYMBOL_TIME) / 1000)
00206 #define AR5K_TURBO_NUM_BITS(_frmlen) (AR5K_TURBO_PLCP_BITS + (_frmlen << 3))
00207 #define AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen) \
00208 howmany(AR5K_TURBO_NUM_BITS(_frmlen), \
00209 AR5K_TURBO_NUM_BITS_PER_SYM(_kbps))
00210 #define AR5K_TURBO_TX_TIME(_kbps, _frmlen) \
00211 AR5K_TURBO_PREAMBLE_TIME + AR5K_TURBO_SIFS_TIME + \
00212 (AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_TURBO_SYMBOL_TIME)
00213
00214 #define AR5K_XR_SIFS_TIME 16
00215 #define AR5K_XR_PLCP_BITS 22
00216 #define AR5K_XR_SYMBOL_TIME 4
00217 #define AR5K_XR_PREAMBLE_TIME(_kbps) (((_kbps) < 1000) ? 173 : 76)
00218 #define AR5K_XR_NUM_BITS_PER_SYM(_kbps) ((_kbps * \
00219 AR5K_XR_SYMBOL_TIME) / 1000)
00220 #define AR5K_XR_NUM_BITS(_frmlen) (AR5K_XR_PLCP_BITS + (_frmlen << 3))
00221 #define AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen) \
00222 howmany(AR5K_XR_NUM_BITS(_frmlen), AR5K_XR_NUM_BITS_PER_SYM(_kbps))
00223 #define AR5K_XR_TX_TIME(_kbps, _frmlen) \
00224 AR5K_XR_PREAMBLE_TIME(_kbps) + AR5K_XR_SIFS_TIME + \
00225 (AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_XR_SYMBOL_TIME)
00226
00227
00228
00229
00230
00231 #define HAL_RX_FILTER_UCAST 0x00000001
00232 #define HAL_RX_FILTER_MCAST 0x00000002
00233 #define HAL_RX_FILTER_BCAST 0x00000004
00234 #define HAL_RX_FILTER_CONTROL 0x00000008
00235 #define HAL_RX_FILTER_BEACON 0x00000010
00236 #define HAL_RX_FILTER_PROM 0x00000020
00237 #define HAL_RX_FILTER_PROBEREQ 0x00000080
00238 #define HAL_RX_FILTER_PHYERR 0x00000100
00239 #define HAL_RX_FILTER_PHYRADAR 0x00000200
00240
00241 typedef struct {
00242 u_int32_t ackrcv_bad;
00243 u_int32_t rts_bad;
00244 u_int32_t rts_good;
00245 u_int32_t fcs_bad;
00246 u_int32_t beacons;
00247 } HAL_MIB_STATS;
00248
00249
00250
00251
00252
00253 #define HAL_BEACON_PERIOD 0x0000ffff
00254 #define HAL_BEACON_ENA 0x00800000
00255 #define HAL_BEACON_RESET_TSF 0x01000000
00256
00257 typedef struct {
00258 u_int32_t bs_next_beacon;
00259 u_int32_t bs_next_dtim;
00260 u_int32_t bs_interval;
00261 u_int8_t bs_dtim_period;
00262 u_int8_t bs_cfpperiod;
00263 u_int16_t bs_cfpmaxduration;
00264 u_int16_t bs_cfp_du_remain;
00265 u_int16_t bs_timoffset;
00266 u_int16_t bs_sleep_duration;
00267 u_int16_t bs_bmiss_threshold;
00268
00269 #define bs_nexttbtt bs_next_beacon
00270 #define bs_intval bs_interval
00271 #define bs_nextdtim bs_next_dtim
00272 #define bs_bmissthreshold bs_bmiss_threshold
00273 #define bs_sleepduration bs_sleep_duration
00274 #define bs_dtimperiod bs_dtim_period
00275
00276 u_int32_t bs_cfpnext;
00277
00278 } HAL_BEACON_STATE;
00279
00280
00281 #ifndef CTRY_DEFAULT
00282 #define CTRY_DEFAULT 0
00283 #endif
00284
00285 #define CHANNEL_2GHZ 0x0080
00286 #define CHANNEL_OFDM 0x0040
00287 #define CHANNEL_TURBO 0x0010
00288 #define CHANNEL_108G (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
00289
00290
00291
00292
00293
00294 typedef enum {
00295 HAL_PM_UNDEFINED = 0,
00296 HAL_PM_AUTO,
00297 HAL_PM_AWAKE,
00298 HAL_PM_FULL_SLEEP,
00299 HAL_PM_NETWORK_SLEEP,
00300 } HAL_POWER_MODE;
00301
00302
00303
00304
00305
00306 typedef enum {
00307 HAL_CIPHER_WEP = 0,
00308 HAL_CIPHER_AES_OCB,
00309 HAL_CIPHER_AES_CCM,
00310 HAL_CIPHER_CKIP,
00311 HAL_CIPHER_TKIP,
00312 HAL_CIPHER_CLR,
00313 HAL_CIPHER_MIC
00314 } HAL_CIPHER;
00315
00316 #define AR5K_KEYVAL_LENGTH_40 5
00317 #define AR5K_KEYVAL_LENGTH_104 13
00318 #define AR5K_KEYVAL_LENGTH_128 16
00319 #define AR5K_KEYVAL_LENGTH_MAX AR5K_KEYVAL_LENGTH_128
00320
00321 typedef struct {
00322 u_int8_t kv_type;
00323 u_int8_t kv_mic[8];
00324 int kv_len;
00325 u_int8_t kv_val[AR5K_KEYVAL_LENGTH_MAX];
00326 } HAL_KEYVAL;
00327
00328
00329 typedef enum {
00330 HAL_CAP_PHYCOUNTERS,
00331 HAL_CAP_CIPHER,
00332 HAL_CAP_TKIP_SPLIT,
00333 HAL_CAP_TPC,
00334 HAL_CAP_TXPOW,
00335 HAL_CAP_BURST,
00336 HAL_CAP_DIVERSITY,
00337 HAL_CAP_VEOL,
00338 HAL_CAP_REG_DMN,
00339 HAL_CAP_NUM_TXQUEUES,
00340 } HAL_CAPABILITY_TYPE;
00341
00342
00343 #define HAL_TXQ_USEDEFAULT ((u_int32_t) -1)
00344 #define HAL_RSSI_EP_MULTIPLIER (1<<7)
00345
00346 #define AR5K_ASSERT_ENTRY(_e, _s) do { \
00347 if (_e >= _s) { \
00348 printk("%s: assert failed\n", __func__); \
00349 return (AH_FALSE); \
00350 } \
00351 } while (0)
00352
00353
00354
00355
00356
00357 #define AR5K_MAX_RATES 32
00358
00359 typedef struct {
00360 u_int8_t valid;
00361 u_int8_t phy;
00362 u_int16_t rateKbps;
00363 u_int8_t rateCode;
00364 u_int8_t shortPreamble;
00365 u_int8_t dot11Rate;
00366 u_int8_t controlRate;
00367
00368 u_int8_t spAckDuration;
00369 u_int8_t lpAckDuration;
00370
00371 #define r_valid valid
00372 #define r_phy phy
00373 #define r_rate_kbps rateKbps
00374 #define r_rate_code rateCode
00375 #define r_short_preamble shortPreamble
00376 #define r_dot11_rate dot11Rate
00377 #define r_control_rate controlRate
00378
00379 } HAL_RATE;
00380
00381 typedef struct {
00382 u_int16_t rateCount;
00383 u_int8_t rateCodeToIndex[AR5K_MAX_RATES];
00384 HAL_RATE info[AR5K_MAX_RATES];
00385
00386 #define rt_rate_count rateCount
00387 #define rt_rate_code_index rateCodeToIndex
00388 #define rt_info info
00389
00390 } HAL_RATE_TABLE;
00391
00392 #define AR5K_RATES_11A { 8, { \
00393 255, 255, 255, 255, 255, 255, 255, 255, 6, 4, 2, 0, \
00394 7, 5, 3, 1, 255, 255, 255, 255, 255, 255, 255, 255, \
00395 255, 255, 255, 255, 255, 255, 255, 255 }, { \
00396 { 1, IEEE80211_T_OFDM, 6000, 11, 0, 140, 0 }, \
00397 { 1, IEEE80211_T_OFDM, 9000, 15, 0, 18, 0 }, \
00398 { 1, IEEE80211_T_OFDM, 12000, 10, 0, 152, 2 }, \
00399 { 1, IEEE80211_T_OFDM, 18000, 14, 0, 36, 2 }, \
00400 { 1, IEEE80211_T_OFDM, 24000, 9, 0, 176, 4 }, \
00401 { 1, IEEE80211_T_OFDM, 36000, 13, 0, 72, 4 }, \
00402 { 1, IEEE80211_T_OFDM, 48000, 8, 0, 96, 4 }, \
00403 { 1, IEEE80211_T_OFDM, 54000, 12, 0, 108, 4 } } \
00404 }
00405
00406 #define AR5K_RATES_11B { 4, { \
00407 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, \
00408 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, \
00409 3, 2, 1, 0, 255, 255, 255, 255 }, { \
00410 { 1, IEEE80211_T_CCK, 1000, 27, 0x00, 130, 0 }, \
00411 { 1, IEEE80211_T_CCK, 2000, 26, 0x04, 132, 1 }, \
00412 { 1, IEEE80211_T_CCK, 5500, 25, 0x04, 139, 1 }, \
00413 { 1, IEEE80211_T_CCK, 11000, 24, 0x04, 150, 1 } } \
00414 }
00415
00416 #define AR5K_RATES_11G { 12, { \
00417 255, 255, 255, 255, 255, 255, 255, 255, 10, 8, 6, 4, \
00418 11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255, \
00419 3, 2, 1, 0, 255, 255, 255, 255 }, { \
00420 { 1, IEEE80211_T_CCK, 1000, 27, 0x00, 2, 0 }, \
00421 { 1, IEEE80211_T_CCK, 2000, 26, 0x04, 4, 1 }, \
00422 { 1, IEEE80211_T_CCK, 5500, 25, 0x04, 11, 1 }, \
00423 { 1, IEEE80211_T_CCK, 11000, 24, 0x04, 22, 1 }, \
00424 { 0, IEEE80211_T_OFDM, 6000, 11, 0, 12, 4 }, \
00425 { 0, IEEE80211_T_OFDM, 9000, 15, 0, 18, 4 }, \
00426 { 1, IEEE80211_T_OFDM, 12000, 10, 0, 24, 6 }, \
00427 { 1, IEEE80211_T_OFDM, 18000, 14, 0, 36, 6 }, \
00428 { 1, IEEE80211_T_OFDM, 24000, 9, 0, 48, 8 }, \
00429 { 1, IEEE80211_T_OFDM, 36000, 13, 0, 72, 8 }, \
00430 { 1, IEEE80211_T_OFDM, 48000, 8, 0, 96, 8 }, \
00431 { 1, IEEE80211_T_OFDM, 54000, 12, 0, 108, 8 } } \
00432 }
00433
00434 #define AR5K_RATES_TURBO { 8, { \
00435 255, 255, 255, 255, 255, 255, 255, 255, 6, 4, 2, 0, \
00436 7, 5, 3, 1, 255, 255, 255, 255, 255, 255, 255, 255, \
00437 255, 255, 255, 255, 255, 255, 255, 255 }, { \
00438 { 1, IEEE80211_T_TURBO, 6000, 11, 0, 140, 0 }, \
00439 { 1, IEEE80211_T_TURBO, 9000, 15, 0, 18, 0 }, \
00440 { 1, IEEE80211_T_TURBO, 12000, 10, 0, 152, 2 }, \
00441 { 1, IEEE80211_T_TURBO, 18000, 14, 0, 36, 2 }, \
00442 { 1, IEEE80211_T_TURBO, 24000, 9, 0, 176, 4 }, \
00443 { 1, IEEE80211_T_TURBO, 36000, 13, 0, 72, 4 }, \
00444 { 1, IEEE80211_T_TURBO, 48000, 8, 0, 96, 4 }, \
00445 { 1, IEEE80211_T_TURBO, 54000, 12, 0, 108, 4 } } \
00446 }
00447
00448 #define AR5K_RATES_XR { 12, { \
00449 255, 3, 1, 255, 255, 255, 2, 0, 10, 8, 6, 4, \
00450 11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255, \
00451 255, 255, 255, 255, 255, 255, 255, 255 }, { \
00452 { 1, IEEE80211_T_XR, 500, 7, 0, 129, 0 }, \
00453 { 1, IEEE80211_T_XR, 1000, 2, 0, 139, 1 }, \
00454 { 1, IEEE80211_T_XR, 2000, 6, 0, 150, 2 }, \
00455 { 1, IEEE80211_T_XR, 3000, 1, 0, 150, 3 }, \
00456 { 1, IEEE80211_T_OFDM, 6000, 11, 0, 140, 4 }, \
00457 { 1, IEEE80211_T_OFDM, 9000, 15, 0, 18, 4 }, \
00458 { 1, IEEE80211_T_OFDM, 12000, 10, 0, 152, 6 }, \
00459 { 1, IEEE80211_T_OFDM, 18000, 14, 0, 36, 6 }, \
00460 { 1, IEEE80211_T_OFDM, 24000, 9, 0, 176, 8 }, \
00461 { 1, IEEE80211_T_OFDM, 36000, 13, 0, 72, 8 }, \
00462 { 1, IEEE80211_T_OFDM, 48000, 8, 0, 96, 8 }, \
00463 { 1, IEEE80211_T_OFDM, 54000, 12, 0, 108, 8 } } \
00464 }
00465
00466 typedef enum {
00467 HAL_RFGAIN_INACTIVE = 0,
00468 HAL_RFGAIN_READ_REQUESTED,
00469 HAL_RFGAIN_NEED_CHANGE,
00470 } HAL_RFGAIN;
00471
00472 typedef struct {
00473 u_int16_t channel;
00474 u_int16_t channelFlags;
00475
00476 #define c_channel channel
00477 #define c_channel_flags channelFlags
00478
00479 } HAL_CHANNEL;
00480
00481 #define HAL_SLOT_TIME_9 396
00482 #define HAL_SLOT_TIME_20 880
00483 #define HAL_SLOT_TIME_MAX 0xffff
00484
00485 #define CHANNEL_A (IEEE80211_CHAN_5GHZ | IEEE80211_CHAN_OFDM)
00486 #define CHANNEL_B (IEEE80211_CHAN_2GHZ | IEEE80211_CHAN_CCK)
00487 #define CHANNEL_G (IEEE80211_CHAN_2GHZ | IEEE80211_CHAN_DYN)
00488 #define CHANNEL_PUREG (IEEE80211_CHAN_2GHZ | IEEE80211_CHAN_DYN)
00489 #define CHANNEL_T (CHANNEL_A | IEEE80211_CHAN_TURBO)
00490 #define CHANNEL_TG (CHANNEL_PUREG | IEEE80211_CHAN_TURBO)
00491 #define CHANNEL_XR (CHANNEL_A | IEEE80211_CHAN_XR)
00492
00493 typedef enum {
00494 HAL_CHIP_5GHZ = IEEE80211_CHAN_5GHZ,
00495 HAL_CHIP_2GHZ = IEEE80211_CHAN_2GHZ,
00496 } HAL_CHIP;
00497
00498
00499
00500
00501
00502
00503 struct ar5k_athchan_2ghz {
00504 u_int32_t a2_flags;
00505 u_int16_t a2_athchan;
00506 };
00507
00508
00509
00510
00511
00512 typedef uint32_t HAL_CTRY_CODE;
00513
00514
00515
00516
00517
00518 #define HAL_INT_RX 0x00000001
00519 #define HAL_INT_RXDESC 0x00000002
00520 #define HAL_INT_RXNOFRM 0x00000008
00521 #define HAL_INT_RXEOL 0x00000010
00522 #define HAL_INT_RXORN 0x00000020
00523 #define HAL_INT_TX 0x00000040
00524 #define HAL_INT_TXDESC 0x00000080
00525 #define HAL_INT_TXURN 0x00000800
00526 #define HAL_INT_MIB 0x00001000
00527 #define HAL_INT_RXPHY 0x00004000
00528 #define HAL_INT_RXKCM 0x00008000
00529 #define HAL_INT_SWBA 0x00010000
00530 #define HAL_INT_BMISS 0x00040000
00531 #define HAL_INT_BNR 0x00100000
00532 #define HAL_INT_GPIO 0x01000000
00533 #define HAL_INT_FATAL 0x40000000
00534 #define HAL_INT_GLOBAL 0x80000000
00535 #define HAL_INT_NOCARD 0xffffffff
00536 #define HAL_INT_COMMON ( \
00537 HAL_INT_RXNOFRM | HAL_INT_RXDESC | HAL_INT_RXEOL | \
00538 HAL_INT_RXORN | HAL_INT_TXURN | HAL_INT_TXDESC | \
00539 HAL_INT_MIB | HAL_INT_RXPHY | HAL_INT_RXKCM | \
00540 HAL_INT_SWBA | HAL_INT_BMISS | HAL_INT_GPIO \
00541 )
00542
00543 typedef u_int32_t HAL_INT;
00544
00545
00546
00547
00548
00549 typedef enum ieee80211_state HAL_LED_STATE;
00550
00551 #define HAL_LED_INIT IEEE80211_S_INIT
00552 #define HAL_LED_SCAN IEEE80211_S_SCAN
00553 #define HAL_LED_AUTH IEEE80211_S_AUTH
00554 #define HAL_LED_ASSOC IEEE80211_S_ASSOC
00555 #define HAL_LED_RUN IEEE80211_S_RUN
00556
00557
00558
00559
00560
00561 #define AR5K_GAIN_CRN_FIX_BITS_5111 4
00562 #define AR5K_GAIN_CRN_FIX_BITS_5112 7
00563 #define AR5K_GAIN_CRN_MAX_FIX_BITS AR5K_GAIN_CRN_FIX_BITS_5112
00564 #define AR5K_GAIN_DYN_ADJUST_HI_MARGIN 15
00565 #define AR5K_GAIN_DYN_ADJUST_LO_MARGIN 20
00566 #define AR5K_GAIN_CCK_PROBE_CORR 5
00567 #define AR5K_GAIN_CCK_OFDM_GAIN_DELTA 15
00568 #define AR5K_GAIN_STEP_COUNT 10
00569 #define AR5K_GAIN_PARAM_TX_CLIP 0
00570 #define AR5K_GAIN_PARAM_PD_90 1
00571 #define AR5K_GAIN_PARAM_PD_84 2
00572 #define AR5K_GAIN_PARAM_GAIN_SEL 3
00573 #define AR5K_GAIN_PARAM_MIX_ORN 0
00574 #define AR5K_GAIN_PARAM_PD_138 1
00575 #define AR5K_GAIN_PARAM_PD_137 2
00576 #define AR5K_GAIN_PARAM_PD_136 3
00577 #define AR5K_GAIN_PARAM_PD_132 4
00578 #define AR5K_GAIN_PARAM_PD_131 5
00579 #define AR5K_GAIN_PARAM_PD_130 6
00580 #define AR5K_GAIN_CHECK_ADJUST(_g) \
00581 ((_g)->g_current <= (_g)->g_low || (_g)->g_current >= (_g)->g_high)
00582
00583 struct ar5k_gain_opt_step {
00584 int16_t gos_param[AR5K_GAIN_CRN_MAX_FIX_BITS];
00585 int32_t gos_gain;
00586 };
00587
00588 struct ar5k_gain_opt {
00589 u_int32_t go_default;
00590 u_int32_t go_steps_count;
00591 const struct ar5k_gain_opt_step go_step[AR5K_GAIN_STEP_COUNT];
00592 };
00593
00594 struct ar5k_gain {
00595 u_int32_t g_step_idx;
00596 u_int32_t g_current;
00597 u_int32_t g_target;
00598 u_int32_t g_low;
00599 u_int32_t g_high;
00600 u_int32_t g_f_corr;
00601 u_int32_t g_active;
00602 const struct ar5k_gain_opt_step *g_step;
00603 };
00604
00605 #define AR5K_AR5111_GAIN_OPT { \
00606 4, \
00607 9, \
00608 { \
00609 { { 4, 1, 1, 1 }, 6 }, \
00610 { { 4, 0, 1, 1 }, 4 }, \
00611 { { 3, 1, 1, 1 }, 3 }, \
00612 { { 4, 0, 0, 1 }, 1 }, \
00613 { { 4, 1, 1, 0 }, 0 }, \
00614 { { 4, 0, 1, 0 }, -2 }, \
00615 { { 3, 1, 1, 0 }, -3 }, \
00616 { { 4, 0, 0, 0 }, -4 }, \
00617 { { 2, 1, 1, 0 }, -6 } \
00618 } \
00619 }
00620
00621 #define AR5K_AR5112_GAIN_OPT { \
00622 1, \
00623 8, \
00624 { \
00625 { { 3, 0, 0, 0, 0, 0, 0 }, 6 }, \
00626 { { 2, 0, 0, 0, 0, 0, 0 }, 0 }, \
00627 { { 1, 0, 0, 0, 0, 0, 0 }, -3 }, \
00628 { { 0, 0, 0, 0, 0, 0, 0 }, -6 }, \
00629 { { 0, 1, 1, 0, 0, 0, 0 }, -8 }, \
00630 { { 0, 1, 1, 0, 1, 1, 0 }, -10 }, \
00631 { { 0, 1, 0, 1, 1, 1, 0 }, -13 }, \
00632 { { 0, 1, 0, 1, 1, 0, 1 }, -16 }, \
00633 } \
00634 }
00635
00636
00637
00638
00639
00640 #define AR5K_EEPROM_MAGIC 0x003d
00641 #define AR5K_EEPROM_MAGIC_VALUE 0x5aa5
00642 #define AR5K_EEPROM_PROTECT 0x003f
00643 #define AR5K_EEPROM_PROTECT_RD_0_31 0x0001
00644 #define AR5K_EEPROM_PROTECT_WR_0_31 0x0002
00645 #define AR5K_EEPROM_PROTECT_RD_32_63 0x0004
00646 #define AR5K_EEPROM_PROTECT_WR_32_63 0x0008
00647 #define AR5K_EEPROM_PROTECT_RD_64_127 0x0010
00648 #define AR5K_EEPROM_PROTECT_WR_64_127 0x0020
00649 #define AR5K_EEPROM_PROTECT_RD_128_191 0x0040
00650 #define AR5K_EEPROM_PROTECT_WR_128_191 0x0080
00651 #define AR5K_EEPROM_PROTECT_RD_192_207 0x0100
00652 #define AR5K_EEPROM_PROTECT_WR_192_207 0x0200
00653 #define AR5K_EEPROM_PROTECT_RD_208_223 0x0400
00654 #define AR5K_EEPROM_PROTECT_WR_208_223 0x0800
00655 #define AR5K_EEPROM_PROTECT_RD_224_239 0x1000
00656 #define AR5K_EEPROM_PROTECT_WR_224_239 0x2000
00657 #define AR5K_EEPROM_PROTECT_RD_240_255 0x4000
00658 #define AR5K_EEPROM_PROTECT_WR_240_255 0x8000
00659 #define AR5K_EEPROM_REG_DOMAIN 0x00bf
00660 #define AR5K_EEPROM_INFO_BASE 0x00c0
00661 #define AR5K_EEPROM_INFO_MAX \
00662 (0x400 - AR5K_EEPROM_INFO_BASE)
00663 #define AR5K_EEPROM_INFO(_n) (AR5K_EEPROM_INFO_BASE + (_n))
00664
00665 #define AR5K_EEPROM_VERSION AR5K_EEPROM_INFO(1)
00666 #define AR5K_EEPROM_VERSION_3_0 0x3000
00667 #define AR5K_EEPROM_VERSION_3_1 0x3001
00668 #define AR5K_EEPROM_VERSION_3_2 0x3002
00669 #define AR5K_EEPROM_VERSION_3_3 0x3003
00670 #define AR5K_EEPROM_VERSION_3_4 0x3004
00671 #define AR5K_EEPROM_VERSION_4_0 0x4000
00672 #define AR5K_EEPROM_VERSION_4_1 0x4001
00673 #define AR5K_EEPROM_VERSION_4_2 0x4002
00674 #define AR5K_EEPROM_VERSION_4_3 0x4003
00675 #define AR5K_EEPROM_VERSION_4_6 0x4006
00676 #define AR5K_EEPROM_VERSION_4_7 0x3007
00677
00678 #define AR5K_EEPROM_MODE_11A 0
00679 #define AR5K_EEPROM_MODE_11B 1
00680 #define AR5K_EEPROM_MODE_11G 2
00681
00682 #define AR5K_EEPROM_HDR AR5K_EEPROM_INFO(2)
00683 #define AR5K_EEPROM_HDR_11A(_v) (((_v) >> AR5K_EEPROM_MODE_11A) & 0x1)
00684 #define AR5K_EEPROM_HDR_11B(_v) (((_v) >> AR5K_EEPROM_MODE_11B) & 0x1)
00685 #define AR5K_EEPROM_HDR_11G(_v) (((_v) >> AR5K_EEPROM_MODE_11G) & 0x1)
00686 #define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v) (((_v) >> 3) & 0x1)
00687 #define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v) (((_v) >> 4) & 0x7f)
00688 #define AR5K_EEPROM_HDR_DEVICE(_v) (((_v) >> 11) & 0x7)
00689 #define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v) (((_v) >> 15) & 0x1)
00690 #define AR5K_EEPROM_HDR_RFKILL(_v) (((_v) >> 14) & 0x1)
00691
00692 #define AR5K_EEPROM_RFKILL_GPIO_SEL 0x0000001c
00693 #define AR5K_EEPROM_RFKILL_GPIO_SEL_S 2
00694 #define AR5K_EEPROM_RFKILL_POLARITY 0x00000002
00695 #define AR5K_EEPROM_RFKILL_POLARITY_S 1
00696
00697
00698 #define AR5K_EEPROM_OFF(_v, _v3_0, _v3_3) \
00699 (((_v) >= AR5K_EEPROM_VERSION_3_3) ? _v3_3 : _v3_0)
00700
00701 #define AR5K_EEPROM_ANT_GAIN(_v) AR5K_EEPROM_OFF(_v, 0x00c4, 0x00c3)
00702 #define AR5K_EEPROM_ANT_GAIN_5GHZ(_v) ((int8_t)(((_v) >> 8) & 0xff))
00703 #define AR5K_EEPROM_ANT_GAIN_2GHZ(_v) ((int8_t)((_v) & 0xff))
00704
00705 #define AR5K_EEPROM_MODES_11A(_v) AR5K_EEPROM_OFF(_v, 0x00c5, 0x00d4)
00706 #define AR5K_EEPROM_MODES_11B(_v) AR5K_EEPROM_OFF(_v, 0x00d0, 0x00f2)
00707 #define AR5K_EEPROM_MODES_11G(_v) AR5K_EEPROM_OFF(_v, 0x00da, 0x010d)
00708 #define AR5K_EEPROM_CTL(_v) AR5K_EEPROM_OFF(_v, 0x00e4, 0x0128)
00709
00710
00711 #define AR5K_EEPROM_OBDB0_2GHZ 0x00ec
00712 #define AR5K_EEPROM_OBDB1_2GHZ 0x00ed
00713
00714
00715 #define AR5K_EEPROM_MISC0 0x00c4
00716 #define AR5K_EEPROM_EARSTART(_v) ((_v) & 0xfff)
00717 #define AR5K_EEPROM_EEMAP(_v) (((_v) >> 14) & 0x3)
00718 #define AR5K_EEPROM_MISC1 0x00c5
00719 #define AR5K_EEPROM_TARGET_PWRSTART(_v) ((_v) & 0xfff)
00720 #define AR5K_EEPROM_HAS32KHZCRYSTAL(_v) (((_v) >> 14) & 0x1)
00721
00722
00723 #define AR5K_EEPROM_EEP_SCALE 100
00724 #define AR5K_EEPROM_EEP_DELTA 10
00725 #define AR5K_EEPROM_N_MODES 3
00726 #define AR5K_EEPROM_N_5GHZ_CHAN 10
00727 #define AR5K_EEPROM_N_2GHZ_CHAN 3
00728 #define AR5K_EEPROM_MAX_CHAN 10
00729 #define AR5K_EEPROM_N_PCDAC 11
00730 #define AR5K_EEPROM_N_TEST_FREQ 8
00731 #define AR5K_EEPROM_N_EDGES 8
00732 #define AR5K_EEPROM_N_INTERCEPTS 11
00733 #define AR5K_EEPROM_FREQ_M(_v) AR5K_EEPROM_OFF(_v, 0x7f, 0xff)
00734 #define AR5K_EEPROM_PCDAC_M 0x3f
00735 #define AR5K_EEPROM_PCDAC_START 1
00736 #define AR5K_EEPROM_PCDAC_STOP 63
00737 #define AR5K_EEPROM_PCDAC_STEP 1
00738 #define AR5K_EEPROM_NON_EDGE_M 0x40
00739 #define AR5K_EEPROM_CHANNEL_POWER 8
00740 #define AR5K_EEPROM_N_OBDB 4
00741 #define AR5K_EEPROM_OBDB_DIS 0xffff
00742 #define AR5K_EEPROM_CHANNEL_DIS 0xff
00743 #define AR5K_EEPROM_SCALE_OC_DELTA(_x) (((_x) * 2) / 10)
00744 #define AR5K_EEPROM_N_CTLS(_v) AR5K_EEPROM_OFF(_v, 16, 32)
00745 #define AR5K_EEPROM_MAX_CTLS 32
00746 #define AR5K_EEPROM_N_XPD_PER_CHANNEL 4
00747 #define AR5K_EEPROM_N_XPD0_POINTS 4
00748 #define AR5K_EEPROM_N_XPD3_POINTS 3
00749 #define AR5K_EEPROM_N_INTERCEPT_10_2GHZ 35
00750 #define AR5K_EEPROM_N_INTERCEPT_10_5GHZ 55
00751 #define AR5K_EEPROM_POWER_M 0x3f
00752 #define AR5K_EEPROM_POWER_MIN 0
00753 #define AR5K_EEPROM_POWER_MAX 3150
00754 #define AR5K_EEPROM_POWER_STEP 50
00755 #define AR5K_EEPROM_POWER_TABLE_SIZE 64
00756 #define AR5K_EEPROM_N_POWER_LOC_11B 4
00757 #define AR5K_EEPROM_N_POWER_LOC_11G 6
00758 #define AR5K_EEPROM_I_GAIN 10
00759 #define AR5K_EEPROM_CCK_OFDM_DELTA 15
00760 #define AR5K_EEPROM_N_IQ_CAL 2
00761
00762 struct ar5k_eeprom_info {
00763 u_int16_t ee_magic;
00764 u_int16_t ee_protect;
00765 u_int16_t ee_regdomain;
00766 u_int16_t ee_version;
00767 u_int16_t ee_header;
00768 u_int16_t ee_ant_gain;
00769 u_int16_t ee_misc0;
00770 u_int16_t ee_misc1;
00771 u_int16_t ee_cck_ofdm_gain_delta;
00772 u_int16_t ee_cck_ofdm_power_delta;
00773 u_int16_t ee_scaled_cck_delta;
00774 u_int16_t ee_tx_clip;
00775 u_int16_t ee_pwd_84;
00776 u_int16_t ee_pwd_90;
00777 u_int16_t ee_gain_select;
00778
00779 u_int16_t ee_i_cal[AR5K_EEPROM_N_MODES];
00780 u_int16_t ee_q_cal[AR5K_EEPROM_N_MODES];
00781 u_int16_t ee_fixed_bias[AR5K_EEPROM_N_MODES];
00782 u_int16_t ee_turbo_max_power[AR5K_EEPROM_N_MODES];
00783 u_int16_t ee_xr_power[AR5K_EEPROM_N_MODES];
00784 u_int16_t ee_switch_settling[AR5K_EEPROM_N_MODES];
00785 u_int16_t ee_ant_tx_rx[AR5K_EEPROM_N_MODES];
00786 u_int16_t ee_ant_control[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PCDAC];
00787 u_int16_t ee_ob[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB];
00788 u_int16_t ee_db[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB];
00789 u_int16_t ee_tx_end2xlna_enable[AR5K_EEPROM_N_MODES];
00790 u_int16_t ee_tx_end2xpa_disable[AR5K_EEPROM_N_MODES];
00791 u_int16_t ee_tx_frm2xpa_enable[AR5K_EEPROM_N_MODES];
00792 u_int16_t ee_thr_62[AR5K_EEPROM_N_MODES];
00793 u_int16_t ee_xlna_gain[AR5K_EEPROM_N_MODES];
00794 u_int16_t ee_xpd[AR5K_EEPROM_N_MODES];
00795 u_int16_t ee_x_gain[AR5K_EEPROM_N_MODES];
00796 u_int16_t ee_i_gain[AR5K_EEPROM_N_MODES];
00797 u_int16_t ee_margin_tx_rx[AR5K_EEPROM_N_MODES];
00798 u_int16_t ee_false_detect[AR5K_EEPROM_N_MODES];
00799 u_int16_t ee_cal_pier[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_2GHZ_CHAN];
00800 u_int16_t ee_channel[AR5K_EEPROM_N_MODES][AR5K_EEPROM_MAX_CHAN];
00801
00802 u_int16_t ee_ctls;
00803 u_int16_t ee_ctl[AR5K_EEPROM_MAX_CTLS];
00804
00805 int16_t ee_noise_floor_thr[AR5K_EEPROM_N_MODES];
00806 int8_t ee_adc_desired_size[AR5K_EEPROM_N_MODES];
00807 int8_t ee_pga_desired_size[AR5K_EEPROM_N_MODES];
00808 };
00809
00810
00811
00812
00813
00814
00815
00816 typedef struct {
00817
00818
00819
00820
00821 u_int16_t cap_mode;
00822
00823
00824
00825
00826 struct {
00827 u_int16_t range_2ghz_min;
00828 u_int16_t range_2ghz_max;
00829 u_int16_t range_5ghz_min;
00830 u_int16_t range_5ghz_max;
00831 } cap_range;
00832
00833
00834
00835
00836 u_int32_t reg_current;
00837 u_int32_t reg_hw;
00838
00839
00840
00841
00842 struct ar5k_eeprom_info cap_eeprom;
00843
00844
00845
00846
00847 struct {
00848 u_int8_t q_tx_num;
00849 } cap_queues;
00850 } ar5k_capabilities_t;
00851
00852
00853
00854
00855
00856 #define AR5K_TXPOWER_OFDM(_r, _v) ( \
00857 ((0 & 1) << ((_v) + 6)) | \
00858 (((hal->ah_txpower.txp_rates[(_r)]) & 0x3f) << (_v)) \
00859 )
00860
00861 #define AR5K_TXPOWER_CCK(_r, _v) ( \
00862 (hal->ah_txpower.txp_rates[(_r)] & 0x3f) << (_v) \
00863 )
00864
00865
00866
00867
00868
00869 struct ath_tx_status {
00870 u_int16_t ts_seqnum;
00871 u_int16_t ts_tstamp;
00872 u_int8_t ts_status;
00873 u_int8_t ts_rate;
00874 int8_t ts_rssi;
00875 u_int8_t ts_shortretry;
00876 u_int8_t ts_longretry;
00877 u_int8_t ts_virtcol;
00878 u_int8_t ts_antenna;
00879 };
00880
00881 #define HAL_TXSTAT_ALTRATE 0x80
00882 #define HAL_TXERR_XRETRY 0x01
00883 #define HAL_TXERR_FILT 0x02
00884 #define HAL_TXERR_FIFO 0x04
00885
00886 struct ath_rx_status {
00887 u_int16_t rs_datalen;
00888 u_int16_t rs_tstamp;
00889 u_int8_t rs_status;
00890 u_int8_t rs_phyerr;
00891 int8_t rs_rssi;
00892 u_int8_t rs_keyix;
00893 u_int8_t rs_rate;
00894 u_int8_t rs_antenna;
00895 u_int8_t rs_more;
00896 };
00897
00898 #define HAL_RXERR_CRC 0x01
00899 #define HAL_RXERR_PHY 0x02
00900 #define HAL_RXERR_FIFO 0x04
00901 #define HAL_RXERR_DECRYPT 0x08
00902 #define HAL_RXERR_MIC 0x10
00903 #define HAL_RXKEYIX_INVALID ((u_int8_t) - 1)
00904 #define HAL_TXKEYIX_INVALID ((u_int32_t) - 1)
00905
00906 #define HAL_PHYERR_UNDERRUN 0x00
00907 #define HAL_PHYERR_TIMING 0x01
00908 #define HAL_PHYERR_PARITY 0x02
00909 #define HAL_PHYERR_RATE 0x03
00910 #define HAL_PHYERR_LENGTH 0x04
00911 #define HAL_PHYERR_RADAR 0x05
00912 #define HAL_PHYERR_SERVICE 0x06
00913 #define HAL_PHYERR_TOR 0x07
00914 #define HAL_PHYERR_OFDM_TIMING 0x11
00915 #define HAL_PHYERR_OFDM_SIGNAL_PARITY 0x12
00916 #define HAL_PHYERR_OFDM_RATE_ILLEGAL 0x13
00917 #define HAL_PHYERR_OFDM_LENGTH_ILLEGAL 0x14
00918 #define HAL_PHYERR_OFDM_POWER_DROP 0x15
00919 #define HAL_PHYERR_OFDM_SERVICE 0x16
00920 #define HAL_PHYERR_OFDM_RESTART 0x17
00921 #define HAL_PHYERR_CCK_TIMING 0x19
00922 #define HAL_PHYERR_CCK_HEADER_CRC 0x1a
00923 #define HAL_PHYERR_CCK_RATE_ILLEGAL 0x1b
00924 #define HAL_PHYERR_CCK_SERVICE 0x1e
00925 #define HAL_PHYERR_CCK_RESTART 0x1f
00926
00927 struct ath_desc {
00928 u_int32_t ds_link;
00929 u_int32_t ds_data;
00930 u_int32_t ds_ctl0;
00931 u_int32_t ds_ctl1;
00932 u_int32_t ds_hw[4];
00933
00934 union {
00935 struct ath_rx_status rx;
00936 struct ath_tx_status tx;
00937 } ds_us;
00938
00939 #define ds_rxstat ds_us.rx
00940 #define ds_txstat ds_us.tx
00941
00942 } __attribute__((__packed__));
00943
00944 #define HAL_RXDESC_INTREQ 0x0020
00945
00946 #define HAL_TXDESC_CLRDMASK 0x0001
00947 #define HAL_TXDESC_NOACK 0x0002
00948 #define HAL_TXDESC_RTSENA 0x0004
00949 #define HAL_TXDESC_CTSENA 0x0008
00950 #define HAL_TXDESC_INTREQ 0x0010
00951 #define HAL_TXDESC_VEOL 0x0020
00952
00953
00954
00955
00956
00957 #define AR5K_HAL_FUNCTION(_hal, _n, _f) (_hal)->ah_##_f = ar5k_##_n##_##_f
00958 #define AR5K_HAL_FUNCTIONS(_t, _n, _a) \
00959
00960
00961 #define AR5K_MAX_GPIO 10
00962 #define AR5K_MAX_RF_BANKS 8
00963
00964 struct ath_hal {
00965 u_int32_t ah_magic;
00966 u_int32_t ah_abi;
00967 u_int16_t ah_device;
00968 u_int16_t ah_sub_vendor;
00969
00970 void *ah_sc;
00971 HAL_BUS_TAG ah_st;
00972 HAL_BUS_HANDLE ah_sh;
00973
00974 HAL_INT ah_imr;
00975
00976 HAL_CTRY_CODE ah_country_code;
00977 HAL_OPMODE ah_op_mode;
00978 HAL_POWER_MODE ah_power_mode;
00979 HAL_CHANNEL ah_current_channel;
00980 HAL_BOOL ah_turbo;
00981 HAL_BOOL ah_calibration;
00982 HAL_BOOL ah_running;
00983 HAL_RFGAIN ah_rf_gain;
00984
00985 #define ah_getcountrycode ah_country_code
00986
00987 HAL_RATE_TABLE ah_rt_11a;
00988 HAL_RATE_TABLE ah_rt_11b;
00989 HAL_RATE_TABLE ah_rt_11g;
00990 HAL_RATE_TABLE ah_rt_turbo;
00991 HAL_RATE_TABLE ah_rt_xr;
00992
00993 u_int32_t ah_mac_version;
00994 u_int16_t ah_mac_revision;
00995 u_int16_t ah_phy_revision;
00996 u_int16_t ah_radio_5ghz_revision;
00997 u_int16_t ah_radio_2ghz_revision;
00998
00999 enum ar5k_version ah_version;
01000 enum ar5k_radio ah_radio;
01001 u_int32_t ah_phy;
01002
01003 HAL_BOOL ah_5ghz;
01004 HAL_BOOL ah_2ghz;
01005
01006 #define ah_macVersion ah_mac_version
01007 #define ah_macRev ah_mac_revision
01008 #define ah_phyRev ah_phy_revision
01009 #define ah_analog5GhzRev ah_radio_5ghz_revision
01010 #define ah_analog2GhzRev ah_radio_2ghz_revision
01011 #define ah_regdomain ah_capabilities.reg_current
01012 #define ah_modes ah_capabilities.cap_mode
01013 #define ah_ee_version ah_capabilities.cap_eeprom.ee_version
01014
01015 u_int32_t ah_atim_window;
01016 u_int32_t ah_aifs;
01017 u_int32_t ah_cw_min;
01018 u_int32_t ah_cw_max;
01019 HAL_BOOL ah_software_retry;
01020 u_int32_t ah_limit_tx_retries;
01021
01022 u_int32_t ah_antenna[AR5K_EEPROM_N_MODES][HAL_ANT_MAX];
01023 HAL_BOOL ah_ant_diversity;
01024
01025 u_int8_t ah_sta_id[IEEE80211_ADDR_LEN];
01026 u_int8_t ah_bssid[IEEE80211_ADDR_LEN];
01027
01028 u_int32_t ah_gpio[AR5K_MAX_GPIO];
01029 int ah_gpio_npins;
01030
01031 ar5k_capabilities_t ah_capabilities;
01032
01033 HAL_TXQ_INFO ah_txq[HAL_NUM_TX_QUEUES];
01034 u_int32_t ah_txq_interrupts;
01035
01036 u_int32_t *ah_rf_banks;
01037 size_t ah_rf_banks_size;
01038 struct ar5k_gain ah_gain;
01039 u_int32_t ah_offset[AR5K_MAX_RF_BANKS];
01040
01041 struct {
01042 u_int16_t txp_pcdac[AR5K_EEPROM_POWER_TABLE_SIZE];
01043 u_int16_t txp_rates[AR5K_MAX_RATES];
01044 int16_t txp_min, txp_max;
01045 HAL_BOOL txp_tpc;
01046 int16_t txp_ofdm;
01047 } ah_txpower;
01048
01049 struct {
01050 HAL_BOOL r_enabled;
01051 int r_last_alert;
01052 HAL_CHANNEL r_last_channel;
01053 } ah_radar;
01054
01055
01056
01057
01058
01059 const HAL_RATE_TABLE * (*ah_getRateTable)(struct ath_hal *, u_int mode);
01060 void (*ah_detach)(struct ath_hal *);
01061 HAL_BOOL (*ah_phyDisable)(struct ath_hal *);
01062
01063
01064 HAL_BOOL (*ah_reset)(struct ath_hal *, HAL_OPMODE,
01065 HAL_CHANNEL *, HAL_BOOL change_channel, HAL_STATUS *status);
01066
01067 HAL_BOOL (*ah_perCalibration)(struct ath_hal*,
01068 HAL_CHANNEL *);
01069
01070
01071
01072 HAL_BOOL (*ah_updateTxTrigLevel)(struct ath_hal*,
01073 HAL_BOOL level);
01074 int (*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE,
01075 const HAL_TXQ_INFO *);
01076 HAL_BOOL (*ah_setTxQueueProps)(struct ath_hal *, int queue,
01077 const HAL_TXQ_INFO *);
01078 HAL_BOOL (*ah_releaseTxQueue)(struct ath_hal *, u_int queue);
01079 HAL_BOOL (*ah_resetTxQueue)(struct ath_hal *, u_int queue);
01080 u_int32_t (*ah_getTxDP)(struct ath_hal *, u_int queue);
01081 HAL_BOOL (*ah_setTxDP)(struct ath_hal *, u_int,
01082 u_int32_t physddr);
01083 HAL_BOOL (*ah_startTxDma)(struct ath_hal *, u_int queue);
01084 HAL_BOOL (*ah_stopTxDma)(struct ath_hal *, u_int queue);
01085 HAL_BOOL (*ah_setupTxDesc)(struct ath_hal *,
01086 struct ath_desc *,
01087 u_int packet_length, u_int header_length, HAL_PKT_TYPE type,
01088 u_int txPower, u_int tx_rate0, u_int tx_tries0, u_int key_index,
01089 u_int antenna_mode, u_int flags, u_int rtscts_rate,
01090 u_int rtscts_duration);
01091 HAL_BOOL (*ah_setupXTxDesc)(struct ath_hal *,
01092 struct ath_desc *,
01093 u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2,
01094 u_int tx_rate3, u_int tx_tries3);
01095 HAL_BOOL (*ah_fillTxDesc)(struct ath_hal *,
01096 struct ath_desc *,
01097 u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg, struct ath_desc *);
01098 HAL_STATUS (*ah_procTxDesc)(struct ath_hal *,
01099 struct ath_desc *);
01100 void (*ah_getTxIntrQueue)(struct ath_hal *, u_int32_t *);
01101
01102
01103
01104 u_int32_t (*ah_getRxDP)(struct ath_hal*);
01105 void (*ah_setRxDP)(struct ath_hal*, u_int32_t rxdp);
01106 void (*ah_enableReceive)(struct ath_hal*);
01107 HAL_BOOL (*ah_stopDmaReceive)(struct ath_hal*);
01108 void (*ah_startPcuReceive)(struct ath_hal*);
01109 void (*ah_stopPcuReceive)(struct ath_hal*);
01110 void (*ah_setMulticastFilter)(struct ath_hal*,
01111 u_int32_t filter0, u_int32_t filter1);
01112 HAL_BOOL (*ah_setMulticastFilterIndex)(struct ath_hal*,
01113 u_int32_t index);
01114 HAL_BOOL (*ah_clrMulticastFilterIndex)(struct ath_hal*,
01115 u_int32_t index);
01116 u_int32_t (*ah_getRxFilter)(struct ath_hal*);
01117 void (*ah_setRxFilter)(struct ath_hal*, u_int32_t);
01118 HAL_BOOL (*ah_setupRxDesc)(struct ath_hal *,
01119 struct ath_desc *, u_int32_t size, u_int flags);
01120 HAL_STATUS (*ah_procRxDesc)(struct ath_hal *,
01121 struct ath_desc *, u_int32_t phyAddr, struct ath_desc *next);
01122 void (*ah_rxMonitor)(struct ath_hal *, HAL_NODE_STATS *);
01123
01124
01125
01126 void (*ah_dump_state)(struct ath_hal *);
01127 HAL_BOOL (*ah_getDiagState)(struct ath_hal *, int request,
01128 const void *args, u_int32_t argsize,
01129 void **result, u_int32_t *resultsize);
01130
01131 void (*ah_get_lladdr)(struct ath_hal *, u_int8_t *);
01132 HAL_BOOL (*ah_set_lladdr)(struct ath_hal *,
01133 const u_int8_t*);
01134 HAL_BOOL (*ah_setRegulatoryDomain)(struct ath_hal*,
01135 u_int16_t, HAL_STATUS *);
01136 void (*ah_setLedState)(struct ath_hal*, int);
01137 void (*ah_writeAssocid)(struct ath_hal*, const u_int8_t *bssid, u_int16_t assocId);
01138 HAL_BOOL (*ah_gpioCfgOutput)(struct ath_hal *,
01139 u_int32_t gpio);
01140 HAL_BOOL (*ah_gpioCfgInput)(struct ath_hal *,
01141 u_int32_t gpio);
01142 u_int32_t (*ah_gpioGet)(struct ath_hal *, u_int32_t gpio);
01143 HAL_BOOL (*ah_gpioSet)(struct ath_hal *, u_int32_t gpio,
01144 u_int32_t val);
01145 void (*ah_gpioSetIntr)(struct ath_hal*, u_int, u_int32_t);
01146 u_int32_t (*ah_getTsf32)(struct ath_hal*);
01147 u_int64_t (*ah_getTsf64)(struct ath_hal*);
01148 void (*ah_resetTsf)(struct ath_hal*);
01149 u_int16_t (*ah_get_regdomain)(struct ath_hal*);
01150 HAL_BOOL (*ah_detectCardPresent)(struct ath_hal*);
01151 void (*ah_updateMibCounters)(struct ath_hal*,
01152 HAL_MIB_STATS*);
01153 HAL_BOOL (*ah_is_cipher_supported)(struct ath_hal*,
01154 HAL_CIPHER);
01155 HAL_RFGAIN (*ah_getRfGain)(struct ath_hal*);
01156
01157
01158
01159
01160
01161
01162 HAL_BOOL (*ah_setSlotTime)(struct ath_hal*, u_int);
01163 u_int (*ah_getSlotTime)(struct ath_hal*);
01164 HAL_BOOL (*ah_setAckTimeout)(struct ath_hal *, u_int);
01165 u_int (*ah_getAckTimeout)(struct ath_hal*);
01166 HAL_BOOL (*ah_setCTSTimeout)(struct ath_hal*, u_int);
01167 u_int (*ah_getCTSTimeout)(struct ath_hal*);
01168
01169
01170 u_int32_t (*ah_getKeyCacheSize)(struct ath_hal*);
01171 HAL_BOOL (*ah_resetKeyCacheEntry)(struct ath_hal*,
01172 u_int16_t);
01173 HAL_BOOL (*ah_isKeyCacheEntryValid)(struct ath_hal *,
01174 u_int16_t);
01175 HAL_BOOL (*ah_set_key)(struct ath_hal*, u_int16_t,
01176 const HAL_KEYVAL *, const u_int8_t *, int);
01177 HAL_BOOL (*ah_set_key_lladdr)(struct ath_hal*,
01178 u_int16_t, const u_int8_t *);
01179
01180
01181
01182 HAL_BOOL (*ah_setPowerMode)(struct ath_hal*,
01183 HAL_POWER_MODE mode,
01184 int set_chip, u_int16_t sleep_duration);
01185 HAL_POWER_MODE (*ah_getPowerMode)(struct ath_hal*);
01186 HAL_BOOL (*ah_query_pspoll_support)(struct ath_hal*);
01187 HAL_BOOL (*ah_initPSPoll)(struct ath_hal*);
01188 HAL_BOOL (*ah_enablePSPoll)(struct ath_hal *, u_int8_t *,
01189 u_int16_t);
01190 HAL_BOOL (*ah_disablePSPoll)(struct ath_hal *);
01191
01192
01193
01194 void (*ah_beaconInit)(struct ath_hal *, u_int32_t nexttbtt,
01195 u_int32_t intval);
01196 void (*ah_setStationBeaconTimers)(struct ath_hal *,
01197 const HAL_BEACON_STATE *);
01198 void (*ah_resetStationBeaconTimers)(struct ath_hal *);
01199 HAL_BOOL (*ah_waitForBeaconDone)(struct ath_hal *,
01200 HAL_BUS_ADDR);
01201
01202
01203
01204 HAL_BOOL (*ah_isInterruptPending)(struct ath_hal *);
01205 HAL_BOOL (*ah_getPendingInterrupts)(struct ath_hal *,
01206 u_int32_t *);
01207 u_int32_t (*ah_getInterrupts)(struct ath_hal *);
01208 HAL_INT (*ah_setInterrupts)(struct ath_hal *, HAL_INT);
01209
01210
01211
01212 HAL_BOOL (*ah_get_capabilities)(struct ath_hal *);
01213 void (*ah_radarlert)(struct ath_hal *, HAL_BOOL enable);
01214
01215
01216 HAL_BOOL (*ah_eeprom_is_busy)(struct ath_hal *);
01217 int (*ah_eeprom_read) (struct ath_hal *, u_int32_t offset, u_int16_t *data);
01218 int (*ah_eeprom_write)(struct ath_hal *, u_int32_t offset, u_int16_t data);
01219
01220 HAL_BOOL (*ah_setTxPowerLimit)(struct ath_hal *, u_int32_t);
01221 HAL_STATUS (*ah_getCapability)(struct ath_hal *,
01222 HAL_CAPABILITY_TYPE, u_int32_t capability,
01223 u_int32_t *result);
01224
01225 void (*ah_procMibEvent)(struct ath_hal *,
01226 const HAL_NODE_STATS *);
01227
01228 HAL_BOOL (*ah_setMacAddress)(struct ath_hal *, const u_int8_t*);
01229 HAL_BOOL (*ah_setCapability)(struct ath_hal *,
01230 HAL_CAPABILITY_TYPE, u_int32_t capability,
01231 u_int32_t setting, HAL_STATUS *);
01232
01233 HAL_BOOL (*ah_setKeyCacheEntry)(struct ath_hal*,
01234 u_int16_t, const HAL_KEYVAL *,
01235 const u_int8_t *, int);
01236 u_int32_t (*ah_numTxPending)(struct ath_hal *, u_int q);
01237 void (*ah_setDefAntenna)(struct ath_hal*, u_int);
01238 u_int (*ah_getDefAntenna)(struct ath_hal*);
01239 void (*ah_getMacAddress)(struct ath_hal *, u_int8_t *);
01240 HAL_BOOL (*ah_updateCTSForBursting)(struct ath_hal *,
01241 struct ath_desc *, struct ath_desc *,
01242 struct ath_desc *, struct ath_desc *,
01243 u_int32_t, u_int32_t);
01244 void (*ah_setPCUConfig)(struct ath_hal *);
01245 HAL_BOOL (*ah_getTxQueueProps)(struct ath_hal *, int q,
01246 HAL_TXQ_INFO *qInfo);
01247
01248
01249 HAL_CTRY_CODE ah_countryCode;
01250
01251 HAL_BOOL (*ah_setKeyCacheEntryMac)(struct ath_hal*,
01252 u_int16_t, const u_int8_t *);
01253 };
01254
01255
01256
01257
01258 enum ar5k_srev_type {
01259 AR5K_VERSION_VER,
01260 AR5K_VERSION_REV,
01261 AR5K_VERSION_RAD
01262 };
01263
01264 struct ar5k_srev_name {
01265 const char *sr_name;
01266 enum ar5k_srev_type sr_type;
01267 u_int sr_val;
01268 };
01269
01270 #define AR5K_SREV_NAME { \
01271 { "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 }, \
01272 { "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 }, \
01273 { "5311a", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A },\
01274 { "5311b", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B },\
01275 { "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 }, \
01276 { "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 }, \
01277 { "xxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN }, \
01278 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 }, \
01279 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 }, \
01280 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 }, \
01281 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 }, \
01282 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 }, \
01283 { "xxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN } \
01284 }
01285
01286 #define AR5K_SREV_UNKNOWN 0xffff
01287
01288 #define AR5K_SREV_REV_FPGA 1
01289 #define AR5K_SREV_REV_PROTO 2
01290 #define AR5K_SREV_REV_PROTOA 3
01291 #define AR5K_SREV_REV_AR5210 4
01292 #define AR5K_SREV_REV_AR5210M 5
01293 #define AR5K_SREV_REV_AR5210M23 7
01294 #define AR5K_SREV_REV_AR521023 8
01295
01296 #define AR5K_SREV_VER_AR5210 0
01297 #define AR5K_SREV_VER_AR5311 1
01298 #define AR5K_SREV_VER_AR5311A 2
01299 #define AR5K_SREV_VER_AR5311B 3
01300 #define AR5K_SREV_VER_AR5211 4
01301 #define AR5K_SREV_VER_AR5212 5
01302
01303 #define AR5K_SREV_RAD_5110 0x00
01304 #define AR5K_SREV_RAD_5111 0x10
01305 #define AR5K_SREV_RAD_5111A 0x15
01306 #define AR5K_SREV_RAD_2111 0x20
01307 #define AR5K_SREV_RAD_5112 0x30
01308 #define AR5K_SREV_RAD_5112A 0x35
01309 #define AR5K_SREV_RAD_2112 0x40
01310 #define AR5K_SREV_RAD_2112A 0x45
01311
01312
01313
01314
01315
01316 #define HAL_ABI_VERSION 0x04090901
01317
01318
01319
01320
01321 #define AR5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__)
01322 #define AR5K_PRINT(fmt) printk("%s: " fmt, __func__)
01323 #ifdef AR5K_DEBUG
01324 #define AR5K_TRACE printk("%s:%d\n", __func__, __LINE__)
01325 #else
01326 #define AR5K_TRACE
01327 #endif
01328 #define AR5K_DELAY(_n) udelay(_n)
01329 #define bcopy(_a, _b, _c) memcpy(_b, _a, _c)
01330 #define bzero(_a, _b) memset(_a, 0, _b)
01331 #ifndef printf
01332 #define printf AR5K_PRINT
01333 #endif
01334 #define AR5K_ELEMENTS(_array) (sizeof(_array) / sizeof(_array[0]))
01335
01336 typedef struct ath_hal * (ar5k_attach_t)
01337 (u_int16_t, void *, HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS *);
01338 typedef HAL_BOOL (ar5k_rfgain_t)
01339 (struct ath_hal *, HAL_CHANNEL *, u_int);
01340
01341
01342
01343
01344
01345 #define AR5K_TUNE_DMA_BEACON_RESP 2
01346 #define AR5K_TUNE_SW_BEACON_RESP 10
01347 #define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0
01348 #define AR5K_TUNE_RADAR_ALERT AH_FALSE
01349 #define AR5K_TUNE_MIN_TX_FIFO_THRES 1
01350 #define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_LEN / 64) + 1)
01351 #define AR5K_TUNE_RSSI_THRES 1792
01352 #define AR5K_TUNE_REGISTER_TIMEOUT 20000
01353 #define AR5K_TUNE_REGISTER_DWELL_TIME 20000
01354 #define AR5K_TUNE_BEACON_INTERVAL 100
01355 #define AR5K_TUNE_AIFS 2
01356 #define AR5K_TUNE_AIFS_11B 2
01357 #define AR5K_TUNE_AIFS_XR 0
01358 #define AR5K_TUNE_CWMIN 15
01359 #define AR5K_TUNE_CWMIN_11B 31
01360 #define AR5K_TUNE_CWMIN_XR 3
01361 #define AR5K_TUNE_CWMAX 1023
01362 #define AR5K_TUNE_CWMAX_11B 1023
01363 #define AR5K_TUNE_CWMAX_XR 7
01364 #define AR5K_TUNE_NOISE_FLOOR -72
01365 #define AR5K_TUNE_MAX_TXPOWER 60
01366 #define AR5K_TUNE_DEFAULT_TXPOWER 30
01367 #define AR5K_TUNE_TPC_TXPOWER AH_TRUE
01368 #define AR5K_TUNE_ANT_DIVERSITY AH_TRUE
01369 #define AR5K_TUNE_HWTXTRIES 4
01370
01371
01372 #define AR5K_TUNE_REGDOMAIN DMN_FCC1_FCCA
01373 #define AR5K_TUNE_CTRY CTRY_DEFAULT
01374
01375
01376
01377
01378
01379 #define AR5K_INIT_MODE ( \
01380 IEEE80211_CHAN_5GHZ | IEEE80211_CHAN_OFDM \
01381 )
01382 #define AR5K_INIT_TX_LATENCY 502
01383 #define AR5K_INIT_USEC 39
01384 #define AR5K_INIT_USEC_TURBO 79
01385 #define AR5K_INIT_USEC_32 31
01386 #define AR5K_INIT_CARR_SENSE_EN 1
01387 #define AR5K_INIT_PROG_IFS 920
01388 #define AR5K_INIT_PROG_IFS_TURBO 960
01389 #define AR5K_INIT_EIFS 3440
01390 #define AR5K_INIT_EIFS_TURBO 6880
01391 #define AR5K_INIT_SLOT_TIME 396
01392 #define AR5K_INIT_SLOT_TIME_TURBO 480
01393 #define AR5K_INIT_ACK_CTS_TIMEOUT 1024
01394 #define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800
01395 #define AR5K_INIT_SIFS 560
01396 #define AR5K_INIT_SIFS_TURBO 480
01397 #define AR5K_INIT_SH_RETRY 10
01398 #define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY
01399 #define AR5K_INIT_SSH_RETRY 32
01400 #define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY
01401 #define AR5K_INIT_TX_RETRY 10
01402 #define AR5K_INIT_TOPS 8
01403 #define AR5K_INIT_RXNOFRM 8
01404 #define AR5K_INIT_RPGTO 0
01405 #define AR5K_INIT_TXNOFRM 0
01406 #define AR5K_INIT_BEACON_PERIOD 65535
01407 #define AR5K_INIT_TIM_OFFSET 0
01408 #define AR5K_INIT_BEACON_EN 0
01409 #define AR5K_INIT_RESET_TSF 0
01410 #define AR5K_INIT_TRANSMIT_LATENCY ( \
01411 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
01412 (AR5K_INIT_USEC) \
01413 )
01414 #define AR5K_INIT_TRANSMIT_LATENCY_TURBO ( \
01415 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
01416 (AR5K_INIT_USEC_TURBO) \
01417 )
01418 #define AR5K_INIT_PROTO_TIME_CNTRL ( \
01419 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) | \
01420 (AR5K_INIT_PROG_IFS) \
01421 )
01422 #define AR5K_INIT_PROTO_TIME_CNTRL_TURBO ( \
01423 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) |\
01424 (AR5K_INIT_PROG_IFS_TURBO) \
01425 )
01426 #define AR5K_INIT_BEACON_CONTROL ( \
01427 (AR5K_INIT_RESET_TSF << 24) | (AR5K_INIT_BEACON_EN << 23) | \
01428 (AR5K_INIT_TIM_OFFSET << 16) | (AR5K_INIT_BEACON_PERIOD) \
01429 )
01430
01431
01432
01433
01434
01435 #define __bswap32(_x) (_x)
01436
01437 #define AR5K_REG_WRITE(_reg, _val) (writel(cpu_to_le32(_val), hal->ah_sh + (_reg)))
01438
01439 #define AR5K_REG_READ(_reg) (le32_to_cpu(readl(hal->ah_sh + (_reg))))
01440
01441 #define AR5K_REG_SM(_val, _flags) \
01442 (((_val) << _flags##_S) & (_flags))
01443 #define AR5K_REG_MS(_val, _flags) \
01444 (((_val) & (_flags)) >> _flags##_S)
01445 #define AR5K_REG_WRITE_BITS(_reg, _flags, _val) \
01446 AR5K_REG_WRITE(_reg, (AR5K_REG_READ(_reg) &~ (_flags)) | \
01447 (((_val) << _flags##_S) & (_flags)))
01448 #define AR5K_REG_MASKED_BITS(_reg, _flags, _mask) \
01449 AR5K_REG_WRITE(_reg, (AR5K_REG_READ(_reg) & (_mask)) | (_flags))
01450 #define AR5K_REG_ENABLE_BITS(_reg, _flags) \
01451 AR5K_REG_WRITE(_reg, AR5K_REG_READ(_reg) | (_flags))
01452 #define AR5K_REG_DISABLE_BITS(_reg, _flags) \
01453 AR5K_REG_WRITE(_reg, AR5K_REG_READ(_reg) &~ (_flags))
01454
01455 #define AR5K_PHY_WRITE(_reg, _val) \
01456 AR5K_REG_WRITE(hal->ah_phy + ((_reg) << 2), _val)
01457 #define AR5K_PHY_READ(_reg) \
01458 AR5K_REG_READ(hal->ah_phy + ((_reg) << 2))
01459
01460 #define AR5K_REG_WAIT(_i) \
01461 if (_i % 64) \
01462 AR5K_DELAY(1);
01463
01464 #define AR5K_EEPROM_READ(_o, _v) { \
01465 if ((ret = hal->ah_eeprom_read(hal, (_o), \
01466 &(_v))) != 0) \
01467 return (ret); \
01468 }
01469 #define AR5K_EEPROM_READ_HDR(_o, _v) \
01470 AR5K_EEPROM_READ(_o, hal->ah_capabilities.cap_eeprom._v); \
01471
01472
01473 #define AR5K_REG_READ_Q(_reg, _queue) \
01474 (AR5K_REG_READ(_reg) & (1 << _queue)) \
01475
01476 #define AR5K_REG_WRITE_Q(_reg, _queue) \
01477 AR5K_REG_WRITE(_reg, (1 << _queue))
01478
01479 #define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \
01480 _reg |= 1 << _queue; \
01481 } while (0)
01482
01483 #define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \
01484 _reg &= ~(1 << _queue); \
01485 } while (0)
01486
01487
01488
01489
01490
01491 #define AR5K_LE_READ_2(_p) \
01492 (((const u_int8_t *)(_p))[0] | (((const u_int8_t *)(_p))[1] << 8))
01493 #define AR5K_LE_READ_4(_p) \
01494 (((const u_int8_t *)(_p))[0] | \
01495 (((const u_int8_t *)(_p))[1] << 8) | \
01496 (((const u_int8_t *)(_p))[2] << 16) | \
01497 (((const u_int8_t *)(_p))[3] << 24))
01498 #define AR5K_LE_WRITE_2(_p, _val) \
01499 ((((u_int8_t *)(_p))[0] = ((u_int32_t)(_val) & 0xff)), \
01500 (((u_int8_t *)(_p))[1] = (((u_int32_t)(_val) >> 8) & 0xff)))
01501 #define AR5K_LE_WRITE_4(_p, _val) \
01502 ((((u_int8_t *)(_p))[0] = ((u_int32_t)(_val) & 0xff)), \
01503 (((u_int8_t *)(_p))[1] = (((u_int32_t)(_val) >> 8) & 0xff)), \
01504 (((u_int8_t *)(_p))[2] = (((u_int32_t)(_val) >> 16) & 0xff)), \
01505 (((u_int8_t *)(_p))[3] = (((u_int32_t)(_val) >> 24) & 0xff)))
01506
01507
01508
01509
01510
01511 struct ar5k_ini {
01512 u_int16_t ini_register;
01513 u_int32_t ini_value;
01514
01515 enum {
01516 AR5K_INI_WRITE = 0,
01517 AR5K_INI_READ = 1,
01518 } ini_mode;
01519 };
01520
01521 #define AR5K_INI_VAL_11A 0
01522 #define AR5K_INI_VAL_11A_TURBO 1
01523 #define AR5K_INI_VAL_11B 2
01524 #define AR5K_INI_VAL_11G 3
01525 #define AR5K_INI_VAL_11G_TURBO 4
01526 #define AR5K_INI_VAL_XR 0
01527 #define AR5K_INI_VAL_MAX 5
01528
01529 #define AR5K_INI_PHY_5111 0
01530 #define AR5K_INI_PHY_5112 1
01531 #define AR5K_INI_PHY_511X 1
01532
01533 #define AR5K_AR5111_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS
01534 #define AR5K_AR5112_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS
01535
01536 struct ar5k_ini_rf {
01537 u_int8_t rf_bank;
01538 u_int16_t rf_register;
01539 u_int32_t rf_value[5];
01540 };
01541
01542 #define AR5K_AR5111_INI_RF { \
01543 { 0, 0x989c, \
01544 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
01545 { 0, 0x989c, \
01546 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
01547 { 0, 0x989c, \
01548 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
01549 { 0, 0x989c, \
01550 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
01551 { 0, 0x989c, \
01552 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
01553 { 0, 0x989c, \
01554 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
01555 { 0, 0x989c, \
01556 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
01557 { 0, 0x989c, \
01558 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
01559 { 0, 0x989c, \
01560 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
01561 { 0, 0x989c, \
01562 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
01563 { 0, 0x989c, \
01564 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
01565 { 0, 0x989c, \
01566 { 0x00380000, 0x00380000, 0x00380000, 0x00380000, 0x00380000 } }, \
01567 { 0, 0x989c, \
01568 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
01569 { 0, 0x989c, \
01570 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
01571 { 0, 0x989c, \
01572 { 0x00000000, 0x00000000, 0x000000c0, 0x00000080, 0x00000080 } }, \
01573 { 0, 0x989c, \
01574 { 0x000400f9, 0x000400f9, 0x000400ff, 0x000400fd, 0x000400fd } }, \
01575 { 0, 0x98d4, \
01576 { 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 } }, \
01577 { 1, 0x98d4, \
01578 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \
01579 { 2, 0x98d4, \
01580 { 0x00000010, 0x00000014, 0x00000010, 0x00000010, 0x00000014 } }, \
01581 { 3, 0x98d8, \
01582 { 0x00601068, 0x00601068, 0x00601068, 0x00601068, 0x00601068 } }, \
01583 { 6, 0x989c, \
01584 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
01585 { 6, 0x989c, \
01586 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
01587 { 6, 0x989c, \
01588 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
01589 { 6, 0x989c, \
01590 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
01591 { 6, 0x989c, \
01592 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
01593 { 6, 0x989c, \
01594 { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } }, \
01595 { 6, 0x989c, \
01596 { 0x04000000, 0x04000000, 0x04000000, 0x04000000, 0x04000000 } }, \
01597 { 6, 0x989c, \
01598 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
01599 { 6, 0x989c, \
01600 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
01601 { 6, 0x989c, \
01602 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
01603 { 6, 0x989c, \
01604 { 0x00000000, 0x00000000, 0x0a000000, 0x00000000, 0x00000000 } }, \
01605 { 6, 0x989c, \
01606 { 0x003800c0, 0x00380080, 0x023800c0, 0x003800c0, 0x003800c0 } }, \
01607 { 6, 0x989c, \
01608 { 0x00020006, 0x00020006, 0x00000006, 0x00020006, 0x00020006 } }, \
01609 { 6, 0x989c, \
01610 { 0x00000089, 0x00000089, 0x00000089, 0x00000089, 0x00000089 } }, \
01611 { 6, 0x989c, \
01612 { 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0 } }, \
01613 { 6, 0x989c, \
01614 { 0x00040007, 0x00040007, 0x00040007, 0x00040007, 0x00040007 } }, \
01615 { 6, 0x98d4, \
01616 { 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a } }, \
01617 { 7, 0x989c, \
01618 { 0x00000040, 0x00000048, 0x00000040, 0x00000040, 0x00000040 } }, \
01619 { 7, 0x989c, \
01620 { 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 } }, \
01621 { 7, 0x989c, \
01622 { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } }, \
01623 { 7, 0x989c, \
01624 { 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f } }, \
01625 { 7, 0x989c, \
01626 { 0x000000f1, 0x000000f1, 0x00000061, 0x000000f1, 0x000000f1 } }, \
01627 { 7, 0x989c, \
01628 { 0x0000904f, 0x0000904f, 0x0000904c, 0x0000904f, 0x0000904f } }, \
01629 { 7, 0x989c, \
01630 { 0x0000125a, 0x0000125a, 0x0000129a, 0x0000125a, 0x0000125a } }, \
01631 { 7, 0x98cc, \
01632 { 0x0000000e, 0x0000000e, 0x0000000f, 0x0000000e, 0x0000000e } }, \
01633 }
01634
01635 #define AR5K_AR5112_INI_RF { \
01636 { 1, 0x98d4, \
01637 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \
01638 { 2, 0x98d0, \
01639 { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } }, \
01640 { 3, 0x98dc, \
01641 { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } }, \
01642 { 6, 0x989c, \
01643 { 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000 } }, \
01644 { 6, 0x989c, \
01645 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
01646 { 6, 0x989c, \
01647 { 0x00800000, 0x00800000, 0x00800000, 0x00800000, 0x00800000 } }, \
01648 { 6, 0x989c, \
01649 { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } }, \
01650 { 6, 0x989c, \
01651 { 0x00010000, 0x00010000, 0x00010000, 0x00010000, 0x00010000 } }, \
01652 { 6, 0x989c, \
01653 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
01654 { 6, 0x989c, \
01655 { 0x00180000, 0x00180000, 0x00180000, 0x00180000, 0x00180000 } }, \
01656 { 6, 0x989c, \
01657 { 0x00600000, 0x00600000, 0x006e0000, 0x006e0000, 0x006e0000 } }, \
01658 { 6, 0x989c, \
01659 { 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000 } }, \
01660 { 6, 0x989c, \
01661 { 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000 } }, \
01662 { 6, 0x989c, \
01663 { 0x04480000, 0x04480000, 0x04480000, 0x04480000, 0x04480000 } }, \
01664 { 6, 0x989c, \
01665 { 0x00220000, 0x00220000, 0x00220000, 0x00220000, 0x00220000 } }, \
01666 { 6, 0x989c, \
01667 { 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000 } }, \
01668 { 6, 0x989c, \
01669 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
01670 { 6, 0x989c, \
01671 { 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000 } }, \
01672 { 6, 0x989c, \
01673 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \
01674 { 6, 0x989c, \
01675 { 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000 } }, \
01676 { 6, 0x989c, \
01677 { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } }, \
01678 { 6, 0x989c, \
01679 { 0x02190000, 0x02190000, 0x02190000, 0x02190000, 0x02190000 } }, \
01680 { 6, 0x989c, \
01681 { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } }, \
01682 { 6, 0x989c, \
01683 { 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000 } }, \
01684 { 6, 0x989c, \
01685 { 0x00990000, 0x00990000, 0x00990000, 0x00990000, 0x00990000 } }, \
01686 { 6, 0x989c, \
01687 { 0x00500000, 0x00500000, 0x00500000, 0x00500000, 0x00500000 } }, \
01688 { 6, 0x989c, \
01689 { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } }, \
01690 { 6, 0x989c, \
01691 { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } }, \
01692 { 6, 0x989c, \
01693 { 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000 } }, \
01694 { 6, 0x989c, \
01695 { 0x01740000, 0x01740000, 0x01740000, 0x01740000, 0x01740000 } }, \
01696 { 6, 0x989c, \
01697 { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } }, \
01698 { 6, 0x989c, \
01699 { 0x86280000, 0x86280000, 0x86280000, 0x86280000, 0x86280000 } }, \
01700 { 6, 0x989c, \
01701 { 0x31840000, 0x31840000, 0x31840000, 0x31840000, 0x31840000 } }, \
01702 { 6, 0x989c, \
01703 { 0x00f20080, 0x00f20080, 0x00f20080, 0x00f20080, 0x00f20080 } }, \
01704 { 6, 0x989c, \
01705 { 0x00070019, 0x00070019, 0x00070019, 0x00070019, 0x00070019 } }, \
01706 { 6, 0x989c, \
01707 { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \
01708 { 6, 0x989c, \
01709 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
01710 { 6, 0x989c, \
01711 { 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2 } }, \
01712 { 6, 0x989c, \
01713 { 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084 } }, \
01714 { 6, 0x989c, \
01715 { 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4 } }, \
01716 { 6, 0x989c, \
01717 { 0x00119220, 0x00119220, 0x00119220, 0x00119220, 0x00119220 } }, \
01718 { 6, 0x989c, \
01719 { 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800 } }, \
01720 { 6, 0x98d8, \
01721 { 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230 } }, \
01722 { 7, 0x989c, \
01723 { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } }, \
01724 { 7, 0x989c, \
01725 { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } }, \
01726 { 7, 0x989c, \
01727 { 0x00000012, 0x00000012, 0x00000012, 0x00000012, 0x00000012 } }, \
01728 { 7, 0x989c, \
01729 { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } }, \
01730 { 7, 0x989c, \
01731 { 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9 } }, \
01732 { 7, 0x989c, \
01733 { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } }, \
01734 { 7, 0x989c, \
01735 { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } }, \
01736 { 7, 0x989c, \
01737 { 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2 } }, \
01738 { 7, 0x989c, \
01739 { 0x00000052, 0x00000052, 0x00000052, 0x00000052, 0x00000052 } }, \
01740 { 7, 0x989c, \
01741 { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } }, \
01742 { 7, 0x989c, \
01743 { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } }, \
01744 { 7, 0x989c, \
01745 { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } }, \
01746 { 7, 0x98c4, \
01747 { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \
01748 }
01749
01750 struct ar5k_ini_rfgain {
01751 u_int16_t rfg_register;
01752 u_int32_t rfg_value[2][2];
01753
01754 #define AR5K_INI_RFGAIN_5GHZ 0
01755 #define AR5K_INI_RFGAIN_2GHZ 1
01756 };
01757
01758 #define AR5K_INI_RFGAIN { \
01759 { 0x9a00, { \
01760 { 0x000001a9, 0x00000000 }, { 0x00000007, 0x00000007 } } }, \
01761 { 0x9a04, { \
01762 { 0x000001e9, 0x00000040 }, { 0x00000047, 0x00000047 } } }, \
01763 { 0x9a08, { \
01764 { 0x00000029, 0x00000080 }, { 0x00000087, 0x00000087 } } }, \
01765 { 0x9a0c, { \
01766 { 0x00000069, 0x00000150 }, { 0x000001a0, 0x000001a0 } } }, \
01767 { 0x9a10, { \
01768 { 0x00000199, 0x00000190 }, { 0x000001e0, 0x000001e0 } } }, \
01769 { 0x9a14, { \
01770 { 0x000001d9, 0x000001d0 }, { 0x00000020, 0x00000020 } } }, \
01771 { 0x9a18, { \
01772 { 0x00000019, 0x00000010 }, { 0x00000060, 0x00000060 } } }, \
01773 { 0x9a1c, { \
01774 { 0x00000059, 0x00000044 }, { 0x000001a1, 0x000001a1 } } }, \
01775 { 0x9a20, { \
01776 { 0x00000099, 0x00000084 }, { 0x000001e1, 0x000001e1 } } }, \
01777 { 0x9a24, { \
01778 { 0x000001a5, 0x00000148 }, { 0x00000021, 0x00000021 } } }, \
01779 { 0x9a28, { \
01780 { 0x000001e5, 0x00000188 }, { 0x00000061, 0x00000061 } } }, \
01781 { 0x9a2c, { \
01782 { 0x00000025, 0x000001c8 }, { 0x00000162, 0x00000162 } } }, \
01783 { 0x9a30, { \
01784 { 0x000001c8, 0x00000014 }, { 0x000001a2, 0x000001a2 } } }, \
01785 { 0x9a34, { \
01786 { 0x00000008, 0x00000042 }, { 0x000001e2, 0x000001e2 } } }, \
01787 { 0x9a38, { \
01788 { 0x00000048, 0x00000082 }, { 0x00000022, 0x00000022 } } }, \
01789 { 0x9a3c, { \
01790 { 0x00000088, 0x00000178 }, { 0x00000062, 0x00000062 } } }, \
01791 { 0x9a40, { \
01792 { 0x00000198, 0x000001b8 }, { 0x00000163, 0x00000163 } } }, \
01793 { 0x9a44, { \
01794 { 0x000001d8, 0x000001f8 }, { 0x000001a3, 0x000001a3 } } }, \
01795 { 0x9a48, { \
01796 { 0x00000018, 0x00000012 }, { 0x000001e3, 0x000001e3 } } }, \
01797 { 0x9a4c, { \
01798 { 0x00000058, 0x00000052 }, { 0x00000023, 0x00000023 } } }, \
01799 { 0x9a50, { \
01800 { 0x00000098, 0x00000092 }, { 0x00000063, 0x00000063 } } }, \
01801 { 0x9a54, { \
01802 { 0x000001a4, 0x0000017c }, { 0x00000184, 0x00000184 } } }, \
01803 { 0x9a58, { \
01804 { 0x000001e4, 0x000001bc }, { 0x000001c4, 0x000001c4 } } }, \
01805 { 0x9a5c, { \
01806 { 0x00000024, 0x000001fc }, { 0x00000004, 0x00000004 } } }, \
01807 { 0x9a60, { \
01808 { 0x00000064, 0x0000000a }, { 0x000001ea, 0x0000000b } } }, \
01809 { 0x9a64, { \
01810 { 0x000000a4, 0x0000004a }, { 0x0000002a, 0x0000004b } } }, \
01811 { 0x9a68, { \
01812 { 0x000000e4, 0x0000008a }, { 0x0000006a, 0x0000008b } } }, \
01813 { 0x9a6c, { \
01814 { 0x0000010a, 0x0000015a }, { 0x000000aa, 0x000001ac } } }, \
01815 { 0x9a70, { \
01816 { 0x0000014a, 0x0000019a }, { 0x000001ab, 0x000001ec } } }, \
01817 { 0x9a74, { \
01818 { 0x0000018a, 0x000001da }, { 0x000001eb, 0x0000002c } } }, \
01819 { 0x9a78, { \
01820 { 0x000001ca, 0x0000000e }, { 0x0000002b, 0x00000012 } } }, \
01821 { 0x9a7c, { \
01822 { 0x0000000a, 0x0000004e }, { 0x0000006b, 0x00000052 } } }, \
01823 { 0x9a80, { \
01824 { 0x0000004a, 0x0000008e }, { 0x000000ab, 0x00000092 } } }, \
01825 { 0x9a84, { \
01826 { 0x0000008a, 0x0000015e }, { 0x000001ac, 0x00000193 } } }, \
01827 { 0x9a88, { \
01828 { 0x000001ba, 0x0000019e }, { 0x000001ec, 0x000001d3 } } }, \
01829 { 0x9a8c, { \
01830 { 0x000001fa, 0x000001de }, { 0x0000002c, 0x00000013 } } }, \
01831 { 0x9a90, { \
01832 { 0x0000003a, 0x00000009 }, { 0x0000003a, 0x00000053 } } }, \
01833 { 0x9a94, { \
01834 { 0x0000007a, 0x00000049 }, { 0x0000007a, 0x00000093 } } }, \
01835 { 0x9a98, { \
01836 { 0x00000186, 0x00000089 }, { 0x000000ba, 0x00000194 } } }, \
01837 { 0x9a9c, { \
01838 { 0x000001c6, 0x00000179 }, { 0x000001bb, 0x000001d4 } } }, \
01839 { 0x9aa0, { \
01840 { 0x00000006, 0x000001b9 }, { 0x000001fb, 0x00000014 } } }, \
01841 { 0x9aa4, { \
01842 { 0x00000046, 0x000001f9 }, { 0x0000003b, 0x0000003a } } }, \
01843 { 0x9aa8, { \
01844 { 0x00000086, 0x00000039 }, { 0x0000007b, 0x0000007a } } }, \
01845 { 0x9aac, { \
01846 { 0x000000c6, 0x00000079 }, { 0x000000bb, 0x000000ba } } }, \
01847 { 0x9ab0, { \
01848 { 0x000000c6, 0x000000b9 }, { 0x000001bc, 0x000001bb } } }, \
01849 { 0x9ab4, { \
01850 { 0x000000c6, 0x000001bd }, { 0x000001fc, 0x000001fb } } }, \
01851 { 0x9ab8, { \
01852 { 0x000000c6, 0x000001fd }, { 0x0000003c, 0x0000003b } } }, \
01853 { 0x9abc, { \
01854 { 0x000000c6, 0x0000003d }, { 0x0000007c, 0x0000007b } } }, \
01855 { 0x9ac0, { \
01856 { 0x000000c6, 0x0000007d }, { 0x000000bc, 0x000000bb } } }, \
01857 { 0x9ac4, { \
01858 { 0x000000c6, 0x000000bd }, { 0x000000fc, 0x000001bc } } }, \
01859 { 0x9ac8, { \
01860 { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000001fc } } }, \
01861 { 0x9acc, { \
01862 { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x0000003c } } }, \
01863 { 0x9ad0, { \
01864 { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x0000007c } } }, \
01865 { 0x9ad4, { \
01866 { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000bc } } }, \
01867 { 0x9ad8, { \
01868 { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \
01869 { 0x9adc, { \
01870 { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \
01871 { 0x9ae0, { \
01872 { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \
01873 { 0x9ae4, { \
01874 { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \
01875 { 0x9ae8, { \
01876 { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \
01877 { 0x9aec, { \
01878 { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \
01879 { 0x9af0, { \
01880 { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \
01881 { 0x9af4, { \
01882 { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \
01883 { 0x9af8, { \
01884 { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \
01885 { 0x9afc, { \
01886 { 0x000000c6, 0x000000fd }, { 0x000000fc, 0x000000fc } } }, \
01887 }
01888
01889
01890
01891
01892
01893 const char *ath_hal_probe(u_int16_t, u_int16_t);
01894
01895 struct ath_hal * _ath_hal_attach(u_int16_t devid, HAL_SOFTC sc, HAL_BUS_TAG t, HAL_BUS_HANDLE h, void* s);
01896
01897 struct ath_hal *ath_hal_attach(u_int16_t device, HAL_SOFTC sc, HAL_BUS_TAG,
01898 HAL_BUS_HANDLE, HAL_STATUS *);
01899
01900 void ath_hal_detach(struct ath_hal *ah);
01901
01902 u_int16_t ath_hal_computetxtime(struct ath_hal *,
01903 const HAL_RATE_TABLE *, u_int32_t, u_int16_t, HAL_BOOL);
01904
01905 u_int ath_hal_mhz2ieee(u_int, u_int);
01906 u_int ath_hal_ieee2mhz(u_int, u_int);
01907
01908 HAL_BOOL ath_hal_init_channels(struct ath_hal *, HAL_CHANNEL *,
01909 u_int, u_int *, HAL_CTRY_CODE, u_int16_t, HAL_BOOL, HAL_BOOL);
01910
01911 extern u_int ath_hal_getwirelessmodes(struct ath_hal*, HAL_CTRY_CODE);
01912 const char *ar5k_printver(enum ar5k_srev_type, u_int);
01913 void ar5k_radar_alert(struct ath_hal *);
01914 u_int32_t ar5k_regdomain_to_ieee(u_int16_t);
01915 u_int16_t ar5k_regdomain_from_ieee(u_int32_t);
01916 u_int16_t ar5k_get_regdomain(struct ath_hal *);
01917
01918 u_int32_t ar5k_bitswap(u_int32_t, u_int);
01919 u_int ar5k_clocktoh(u_int, HAL_BOOL);
01920 u_int ar5k_htoclock(u_int, HAL_BOOL);
01921 void ar5k_rt_copy(HAL_RATE_TABLE *, const HAL_RATE_TABLE *);
01922
01923 HAL_BOOL ar5k_register_timeout(struct ath_hal *, u_int32_t,
01924 u_int32_t, u_int32_t, HAL_BOOL);
01925
01926 int ar5k_eeprom_init(struct ath_hal *);
01927 int ar5k_eeprom_read_mac(struct ath_hal *, u_int8_t *);
01928 HAL_BOOL ar5k_eeprom_regulation_domain(struct ath_hal *,
01929 HAL_BOOL, u_int32_t *);
01930
01931 HAL_BOOL ar5k_channel(struct ath_hal *, HAL_CHANNEL *);
01932 HAL_BOOL ar5k_rfregs(struct ath_hal *, HAL_CHANNEL *, u_int);
01933 u_int32_t ar5k_rfregs_gainf_corr(struct ath_hal *);
01934 HAL_BOOL ar5k_rfregs_gain_readback(struct ath_hal *);
01935 int32_t ar5k_rfregs_gain_adjust(struct ath_hal *);
01936 HAL_BOOL ar5k_rfgain(struct ath_hal *, u_int, u_int);
01937
01938 void ar5k_txpower_table(struct ath_hal *, HAL_CHANNEL *,
01939 int16_t);
01940
01941
01942
01943 #endif
