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00024 #ifndef _AR5K_AR5210_VAR_H
00025 #define _AR5K_AR5210_VAR_H
00026
00027 #include <dev/ic/ar5xxx.h>
00028
00029
00030
00031
00032
00033 #define AR5K_AR5210_MAGIC 0x0000145a
00034 #define AR5K_AR5210_TX_NUM_QUEUES 2
00035
00036 #if BYTE_ORDER == BIG_ENDIAN
00037 #define AR5K_AR5210_INIT_CFG ( \
00038 AR5K_AR5210_CFG_SWTD | AR5K_AR5210_CFG_SWRD \
00039 )
00040 #else
00041 #define AR5K_AR5210_INIT_CFG 0x00000000
00042 #endif
00043
00044
00045
00046
00047
00048
00049 struct ar5k_ar5210_rx_desc {
00050
00051
00052
00053 u_int32_t rx_control_0;
00054
00055 #define AR5K_AR5210_DESC_RX_CTL0 0x00000000
00056
00057
00058
00059
00060 u_int32_t rx_control_1;
00061
00062 #define AR5K_AR5210_DESC_RX_CTL1_BUF_LEN 0x00000fff
00063 #define AR5K_AR5210_DESC_RX_CTL1_INTREQ 0x00002000
00064 } __attribute__((__packed__));
00065
00066 struct ar5k_ar5210_rx_status {
00067
00068
00069
00070 u_int32_t rx_status_0;
00071
00072 #define AR5K_AR5210_DESC_RX_STATUS0_DATA_LEN 0x00000fff
00073 #define AR5K_AR5210_DESC_RX_STATUS0_MORE 0x00001000
00074 #define AR5K_AR5210_DESC_RX_STATUS0_RECEIVE_ANTENNA 0x00004000
00075 #define AR5K_AR5210_DESC_RX_STATUS0_RECEIVE_RATE 0x00078000
00076 #define AR5K_AR5210_DESC_RX_STATUS0_RECEIVE_RATE_S 15
00077 #define AR5K_AR5210_DESC_RX_STATUS0_RECEIVE_SIGNAL 0x07f80000
00078 #define AR5K_AR5210_DESC_RX_STATUS0_RECEIVE_SIGNAL_S 19
00079
00080
00081
00082
00083 u_int32_t rx_status_1;
00084
00085 #define AR5K_AR5210_DESC_RX_STATUS1_DONE 0x00000001
00086 #define AR5K_AR5210_DESC_RX_STATUS1_FRAME_RECEIVE_OK 0x00000002
00087 #define AR5K_AR5210_DESC_RX_STATUS1_CRC_ERROR 0x00000004
00088 #define AR5K_AR5210_DESC_RX_STATUS1_FIFO_OVERRUN 0x00000008
00089 #define AR5K_AR5210_DESC_RX_STATUS1_DECRYPT_CRC_ERROR 0x00000010
00090 #define AR5K_AR5210_DESC_RX_STATUS1_PHY_ERROR 0x000000e0
00091 #define AR5K_AR5210_DESC_RX_STATUS1_PHY_ERROR_S 5
00092 #define AR5K_AR5210_DESC_RX_STATUS1_KEY_INDEX_VALID 0x00000100
00093 #define AR5K_AR5210_DESC_RX_STATUS1_KEY_INDEX 0x00007e00
00094 #define AR5K_AR5210_DESC_RX_STATUS1_KEY_INDEX_S 9
00095 #define AR5K_AR5210_DESC_RX_STATUS1_RECEIVE_TIMESTAMP 0x0fff8000
00096 #define AR5K_AR5210_DESC_RX_STATUS1_RECEIVE_TIMESTAMP_S 15
00097 #define AR5K_AR5210_DESC_RX_STATUS1_KEY_CACHE_MISS 0x10000000
00098 } __attribute__((__packed__));
00099
00100 #define AR5K_AR5210_DESC_RX_PHY_ERROR_NONE 0x00
00101 #define AR5K_AR5210_DESC_RX_PHY_ERROR_TIMING 0x20
00102 #define AR5K_AR5210_DESC_RX_PHY_ERROR_PARITY 0x40
00103 #define AR5K_AR5210_DESC_RX_PHY_ERROR_RATE 0x60
00104 #define AR5K_AR5210_DESC_RX_PHY_ERROR_LENGTH 0x80
00105 #define AR5K_AR5210_DESC_RX_PHY_ERROR_64QAM 0xa0
00106 #define AR5K_AR5210_DESC_RX_PHY_ERROR_SERVICE 0xc0
00107 #define AR5K_AR5210_DESC_RX_PHY_ERROR_TRANSMITOVR 0xe0
00108
00109 struct ar5k_ar5210_tx_desc {
00110
00111
00112
00113 u_int32_t tx_control_0;
00114
00115 #define AR5K_AR5210_DESC_TX_CTL0_FRAME_LEN 0x00000fff
00116 #define AR5K_AR5210_DESC_TX_CTL0_HEADER_LEN 0x0003f000
00117 #define AR5K_AR5210_DESC_TX_CTL0_HEADER_LEN_S 12
00118 #define AR5K_AR5210_DESC_TX_CTL0_XMIT_RATE 0x003c0000
00119 #define AR5K_AR5210_DESC_TX_CTL0_XMIT_RATE_S 18
00120 #define AR5K_AR5210_DESC_TX_CTL0_RTSENA 0x00400000
00121 #define AR5K_AR5210_DESC_TX_CTL0_LONG_PACKET 0x00800000
00122 #define AR5K_AR5210_DESC_TX_CTL0_CLRDMASK 0x01000000
00123 #define AR5K_AR5210_DESC_TX_CTL0_ANT_MODE_XMIT 0x02000000
00124 #define AR5K_AR5210_DESC_TX_CTL0_FRAME_TYPE 0x1c000000
00125 #define AR5K_AR5210_DESC_TX_CTL0_FRAME_TYPE_S 26
00126 #define AR5K_AR5210_DESC_TX_CTL0_INTREQ 0x20000000
00127 #define AR5K_AR5210_DESC_TX_CTL0_ENCRYPT_KEY_VALID 0x40000000
00128
00129
00130
00131
00132 u_int32_t tx_control_1;
00133
00134 #define AR5K_AR5210_DESC_TX_CTL1_BUF_LEN 0x00000fff
00135 #define AR5K_AR5210_DESC_TX_CTL1_MORE 0x00001000
00136 #define AR5K_AR5210_DESC_TX_CTL1_ENCRYPT_KEY_INDEX 0x0007e000
00137 #define AR5K_AR5210_DESC_TX_CTL1_ENCRYPT_KEY_INDEX_S 13
00138 #define AR5K_AR5210_DESC_TX_CTL1_RTS_DURATION 0xfff80000
00139 } __attribute__((__packed__));
00140
00141 #define AR5K_AR5210_DESC_TX_FRAME_TYPE_NORMAL 0x00
00142 #define AR5K_AR5210_DESC_TX_FRAME_TYPE_ATIM 0x04
00143 #define AR5K_AR5210_DESC_TX_FRAME_TYPE_PSPOLL 0x08
00144 #define AR5K_AR5210_DESC_TX_FRAME_TYPE_NO_DELAY 0x0c
00145 #define AR5K_AR5210_DESC_TX_FRAME_TYPE_PIFS 0x10
00146
00147 struct ar5k_ar5210_tx_status {
00148
00149
00150
00151 u_int32_t tx_status_0;
00152
00153 #define AR5K_AR5210_DESC_TX_STATUS0_FRAME_XMIT_OK 0x00000001
00154 #define AR5K_AR5210_DESC_TX_STATUS0_EXCESSIVE_RETRIES 0x00000002
00155 #define AR5K_AR5210_DESC_TX_STATUS0_FIFO_UNDERRUN 0x00000004
00156 #define AR5K_AR5210_DESC_TX_STATUS0_FILTERED 0x00000008
00157 #define AR5K_AR5210_DESC_TX_STATUS0_SHORT_RETRY_COUNT 0x000000f0
00158 #define AR5K_AR5210_DESC_TX_STATUS0_SHORT_RETRY_COUNT_S 4
00159 #define AR5K_AR5210_DESC_TX_STATUS0_LONG_RETRY_COUNT 0x00000f00
00160 #define AR5K_AR5210_DESC_TX_STATUS0_LONG_RETRY_COUNT_S 8
00161 #define AR5K_AR5210_DESC_TX_STATUS0_SEND_TIMESTAMP 0xffff0000
00162 #define AR5K_AR5210_DESC_TX_STATUS0_SEND_TIMESTAMP_S 16
00163
00164
00165
00166
00167 u_int32_t tx_status_1;
00168
00169 #define AR5K_AR5210_DESC_TX_STATUS1_DONE 0x00000001
00170 #define AR5K_AR5210_DESC_TX_STATUS1_SEQ_NUM 0x00001ffe
00171 #define AR5K_AR5210_DESC_TX_STATUS1_SEQ_NUM_S 1
00172 #define AR5K_AR5210_DESC_TX_STATUS1_ACK_SIG_STRENGTH 0x001fe000
00173 #define AR5K_AR5210_DESC_TX_STATUS1_ACK_SIG_STRENGTH_S 13
00174 } __attribute__((__packed__));
00175
00176
00177
00178
00179 extern ar5k_attach_t ar5k_ar5210_attach;
00180
00181
00182
00183
00184
00185 #define AR5K_AR5210_INI_MODE(_aifs) { \
00186 { AR5K_AR5210_SLOT_TIME, \
00187 AR5K_INIT_SLOT_TIME, \
00188 AR5K_INIT_SLOT_TIME_TURBO }, \
00189 { AR5K_AR5210_SLOT_TIME, \
00190 AR5K_INIT_ACK_CTS_TIMEOUT, \
00191 AR5K_INIT_ACK_CTS_TIMEOUT_TURBO }, \
00192 { AR5K_AR5210_USEC, \
00193 AR5K_INIT_TRANSMIT_LATENCY, \
00194 AR5K_INIT_TRANSMIT_LATENCY_TURBO}, \
00195 { AR5K_AR5210_IFS0, \
00196 ((AR5K_INIT_SIFS + (_aifs) * AR5K_INIT_SLOT_TIME) \
00197 << AR5K_AR5210_IFS0_DIFS_S) | AR5K_INIT_SIFS, \
00198 ((AR5K_INIT_SIFS_TURBO + (_aifs) * AR5K_INIT_SLOT_TIME_TURBO) \
00199 << AR5K_AR5210_IFS0_DIFS_S) | AR5K_INIT_SIFS_TURBO }, \
00200 { AR5K_AR5210_IFS1, \
00201 AR5K_INIT_PROTO_TIME_CNTRL, \
00202 AR5K_INIT_PROTO_TIME_CNTRL_TURBO }, \
00203 { AR5K_AR5210_PHY(17), \
00204 (AR5K_REG_READ(AR5K_AR5210_PHY(17)) & ~0x7F) | 0x1C, \
00205 (AR5K_REG_READ(AR5K_AR5210_PHY(17)) & ~0x7F) | 0x38 }, \
00206 { AR5K_AR5210_PHY_FC, \
00207 AR5K_AR5210_PHY_FC_SERVICE_ERR | \
00208 AR5K_AR5210_PHY_FC_TXURN_ERR | \
00209 AR5K_AR5210_PHY_FC_ILLLEN_ERR | \
00210 AR5K_AR5210_PHY_FC_ILLRATE_ERR | \
00211 AR5K_AR5210_PHY_FC_PARITY_ERR | \
00212 AR5K_AR5210_PHY_FC_TIMING_ERR | 0x1020, \
00213 AR5K_AR5210_PHY_FC_SERVICE_ERR | \
00214 AR5K_AR5210_PHY_FC_TXURN_ERR | \
00215 AR5K_AR5210_PHY_FC_ILLLEN_ERR | \
00216 AR5K_AR5210_PHY_FC_ILLRATE_ERR | \
00217 AR5K_AR5210_PHY_FC_PARITY_ERR | \
00218 AR5K_AR5210_PHY_FC_TURBO_MODE | \
00219 AR5K_AR5210_PHY_FC_TURBO_SHORT | \
00220 AR5K_AR5210_PHY_FC_TIMING_ERR | 0x2020 }, \
00221 }
00222
00223
00224
00225
00226
00227
00228 #define AR5K_AR5210_INI { \
00229 \
00230 { AR5K_AR5210_TXDP0, 0 }, \
00231 { AR5K_AR5210_TXDP1, 0 }, \
00232 { AR5K_AR5210_RXDP, 0 }, \
00233 { AR5K_AR5210_CR, 0 }, \
00234 { AR5K_AR5210_ISR, 0, AR5K_INI_READ }, \
00235 { AR5K_AR5210_IMR, 0 }, \
00236 { AR5K_AR5210_IER, AR5K_AR5210_IER_DISABLE }, \
00237 { AR5K_AR5210_BSR, 0, AR5K_INI_READ }, \
00238 { AR5K_AR5210_TXCFG, AR5K_AR5210_DMASIZE_128B }, \
00239 { AR5K_AR5210_RXCFG, AR5K_AR5210_DMASIZE_128B }, \
00240 { AR5K_AR5210_CFG, AR5K_AR5210_INIT_CFG }, \
00241 { AR5K_AR5210_TOPS, AR5K_INIT_TOPS }, \
00242 { AR5K_AR5210_RXNOFRM, AR5K_INIT_RXNOFRM }, \
00243 { AR5K_AR5210_RPGTO, AR5K_INIT_RPGTO }, \
00244 { AR5K_AR5210_TXNOFRM, AR5K_INIT_TXNOFRM }, \
00245 { AR5K_AR5210_SFR, 0 }, \
00246 { AR5K_AR5210_MIBC, 0 }, \
00247 { AR5K_AR5210_MISC, 0 }, \
00248 { AR5K_AR5210_RX_FILTER, 0 }, \
00249 { AR5K_AR5210_MCAST_FIL0, 0 }, \
00250 { AR5K_AR5210_MCAST_FIL1, 0 }, \
00251 { AR5K_AR5210_TX_MASK0, 0 }, \
00252 { AR5K_AR5210_TX_MASK1, 0 }, \
00253 { AR5K_AR5210_CLR_TMASK, 0 }, \
00254 { AR5K_AR5210_TRIG_LVL, AR5K_TUNE_MIN_TX_FIFO_THRES }, \
00255 { AR5K_AR5210_DIAG_SW, 0 }, \
00256 { AR5K_AR5210_RSSI_THR, AR5K_TUNE_RSSI_THRES }, \
00257 { AR5K_AR5210_TSF_L32, 0 }, \
00258 { AR5K_AR5210_TIMER0, 0 }, \
00259 { AR5K_AR5210_TIMER1, 0xffffffff }, \
00260 { AR5K_AR5210_TIMER2, 0xffffffff }, \
00261 { AR5K_AR5210_TIMER3, 1 }, \
00262 { AR5K_AR5210_CFP_DUR, 0 }, \
00263 { AR5K_AR5210_CFP_PERIOD, 0 }, \
00264 \
00265 { AR5K_AR5210_PHY(0), 0x00000047 }, \
00266 { AR5K_AR5210_PHY_AGC, 0x00000000 }, \
00267 { AR5K_AR5210_PHY(3), 0x09848ea6 }, \
00268 { AR5K_AR5210_PHY(4), 0x3d32e000 }, \
00269 { AR5K_AR5210_PHY(5), 0x0000076b }, \
00270 { AR5K_AR5210_PHY_ACTIVE, AR5K_AR5210_PHY_DISABLE }, \
00271 { AR5K_AR5210_PHY(8), 0x02020200 }, \
00272 { AR5K_AR5210_PHY(9), 0x00000e0e }, \
00273 { AR5K_AR5210_PHY(10), 0x0a020201 }, \
00274 { AR5K_AR5210_PHY(11), 0x00036ffc }, \
00275 { AR5K_AR5210_PHY(12), 0x00000000 }, \
00276 { AR5K_AR5210_PHY(13), 0x00000e0e }, \
00277 { AR5K_AR5210_PHY(14), 0x00000007 }, \
00278 { AR5K_AR5210_PHY(15), 0x00020100 }, \
00279 { AR5K_AR5210_PHY(16), 0x89630000 }, \
00280 { AR5K_AR5210_PHY(17), 0x1372169c }, \
00281 { AR5K_AR5210_PHY(18), 0x0018b633 }, \
00282 { AR5K_AR5210_PHY(19), 0x1284613c }, \
00283 { AR5K_AR5210_PHY(20), 0x0de8b8e0 }, \
00284 { AR5K_AR5210_PHY(21), 0x00074859 }, \
00285 { AR5K_AR5210_PHY(22), 0x7e80beba }, \
00286 { AR5K_AR5210_PHY(23), 0x313a665e }, \
00287 { AR5K_AR5210_PHY_AGCCTL, 0x00001d08 }, \
00288 { AR5K_AR5210_PHY(25), 0x0001ce00 }, \
00289 { AR5K_AR5210_PHY(26), 0x409a4190 }, \
00290 { AR5K_AR5210_PHY(28), 0x0000000f }, \
00291 { AR5K_AR5210_PHY(29), 0x00000080 }, \
00292 { AR5K_AR5210_PHY(30), 0x00000004 }, \
00293 { AR5K_AR5210_PHY(31), 0x00000018 }, \
00294 { AR5K_AR5210_PHY(64), 0x00000000 }, \
00295 { AR5K_AR5210_PHY(65), 0x00000000 }, \
00296 { AR5K_AR5210_PHY(66), 0x00000000 }, \
00297 { AR5K_AR5210_PHY(67), 0x00800000 }, \
00298 { AR5K_AR5210_PHY(68), 0x00000003 }, \
00299 \
00300 { AR5K_AR5210_BB_GAIN(0), 0x00000000 }, \
00301 { AR5K_AR5210_BB_GAIN(0x01), 0x00000020 }, \
00302 { AR5K_AR5210_BB_GAIN(0x02), 0x00000010 }, \
00303 { AR5K_AR5210_BB_GAIN(0x03), 0x00000030 }, \
00304 { AR5K_AR5210_BB_GAIN(0x04), 0x00000008 }, \
00305 { AR5K_AR5210_BB_GAIN(0x05), 0x00000028 }, \
00306 { AR5K_AR5210_BB_GAIN(0x06), 0x00000028 }, \
00307 { AR5K_AR5210_BB_GAIN(0x07), 0x00000004 }, \
00308 { AR5K_AR5210_BB_GAIN(0x08), 0x00000024 }, \
00309 { AR5K_AR5210_BB_GAIN(0x09), 0x00000014 }, \
00310 { AR5K_AR5210_BB_GAIN(0x0a), 0x00000034 }, \
00311 { AR5K_AR5210_BB_GAIN(0x0b), 0x0000000c }, \
00312 { AR5K_AR5210_BB_GAIN(0x0c), 0x0000002c }, \
00313 { AR5K_AR5210_BB_GAIN(0x0d), 0x00000002 }, \
00314 { AR5K_AR5210_BB_GAIN(0x0e), 0x00000022 }, \
00315 { AR5K_AR5210_BB_GAIN(0x0f), 0x00000012 }, \
00316 { AR5K_AR5210_BB_GAIN(0x10), 0x00000032 }, \
00317 { AR5K_AR5210_BB_GAIN(0x11), 0x0000000a }, \
00318 { AR5K_AR5210_BB_GAIN(0x12), 0x0000002a }, \
00319 { AR5K_AR5210_BB_GAIN(0x13), 0x00000001 }, \
00320 { AR5K_AR5210_BB_GAIN(0x14), 0x00000021 }, \
00321 { AR5K_AR5210_BB_GAIN(0x15), 0x00000011 }, \
00322 { AR5K_AR5210_BB_GAIN(0x16), 0x00000031 }, \
00323 { AR5K_AR5210_BB_GAIN(0x17), 0x00000009 }, \
00324 { AR5K_AR5210_BB_GAIN(0x18), 0x00000029 }, \
00325 { AR5K_AR5210_BB_GAIN(0x19), 0x00000005 }, \
00326 { AR5K_AR5210_BB_GAIN(0x1a), 0x00000025 }, \
00327 { AR5K_AR5210_BB_GAIN(0x1b), 0x00000015 }, \
00328 { AR5K_AR5210_BB_GAIN(0x1c), 0x00000035 }, \
00329 { AR5K_AR5210_BB_GAIN(0x1d), 0x0000000d }, \
00330 { AR5K_AR5210_BB_GAIN(0x1e), 0x0000002d }, \
00331 { AR5K_AR5210_BB_GAIN(0x1f), 0x00000003 }, \
00332 { AR5K_AR5210_BB_GAIN(0x20), 0x00000023 }, \
00333 { AR5K_AR5210_BB_GAIN(0x21), 0x00000013 }, \
00334 { AR5K_AR5210_BB_GAIN(0x22), 0x00000033 }, \
00335 { AR5K_AR5210_BB_GAIN(0x23), 0x0000000b }, \
00336 { AR5K_AR5210_BB_GAIN(0x24), 0x0000002b }, \
00337 { AR5K_AR5210_BB_GAIN(0x25), 0x00000007 }, \
00338 { AR5K_AR5210_BB_GAIN(0x26), 0x00000027 }, \
00339 { AR5K_AR5210_BB_GAIN(0x27), 0x00000017 }, \
00340 { AR5K_AR5210_BB_GAIN(0x28), 0x00000037 }, \
00341 { AR5K_AR5210_BB_GAIN(0x29), 0x0000000f }, \
00342 { AR5K_AR5210_BB_GAIN(0x2a), 0x0000002f }, \
00343 { AR5K_AR5210_BB_GAIN(0x2b), 0x0000002f }, \
00344 { AR5K_AR5210_BB_GAIN(0x2c), 0x0000002f }, \
00345 { AR5K_AR5210_BB_GAIN(0x2d), 0x0000002f }, \
00346 { AR5K_AR5210_BB_GAIN(0x2e), 0x0000002f }, \
00347 { AR5K_AR5210_BB_GAIN(0x2f), 0x0000002f }, \
00348 { AR5K_AR5210_BB_GAIN(0x30), 0x0000002f }, \
00349 { AR5K_AR5210_BB_GAIN(0x31), 0x0000002f }, \
00350 { AR5K_AR5210_BB_GAIN(0x32), 0x0000002f }, \
00351 { AR5K_AR5210_BB_GAIN(0x33), 0x0000002f }, \
00352 { AR5K_AR5210_BB_GAIN(0x34), 0x0000002f }, \
00353 { AR5K_AR5210_BB_GAIN(0x35), 0x0000002f }, \
00354 { AR5K_AR5210_BB_GAIN(0x36), 0x0000002f }, \
00355 { AR5K_AR5210_BB_GAIN(0x37), 0x0000002f }, \
00356 { AR5K_AR5210_BB_GAIN(0x38), 0x0000002f }, \
00357 { AR5K_AR5210_BB_GAIN(0x39), 0x0000002f }, \
00358 { AR5K_AR5210_BB_GAIN(0x3a), 0x0000002f }, \
00359 { AR5K_AR5210_BB_GAIN(0x3b), 0x0000002f }, \
00360 { AR5K_AR5210_BB_GAIN(0x3c), 0x0000002f }, \
00361 { AR5K_AR5210_BB_GAIN(0x3d), 0x0000002f }, \
00362 { AR5K_AR5210_BB_GAIN(0x3e), 0x0000002f }, \
00363 { AR5K_AR5210_BB_GAIN(0x3f), 0x0000002f }, \
00364 \
00365 { AR5K_AR5210_RF_GAIN(0), 0x0000001d }, \
00366 { AR5K_AR5210_RF_GAIN(0x01), 0x0000005d }, \
00367 { AR5K_AR5210_RF_GAIN(0x02), 0x0000009d }, \
00368 { AR5K_AR5210_RF_GAIN(0x03), 0x000000dd }, \
00369 { AR5K_AR5210_RF_GAIN(0x04), 0x0000011d }, \
00370 { AR5K_AR5210_RF_GAIN(0x05), 0x00000021 }, \
00371 { AR5K_AR5210_RF_GAIN(0x06), 0x00000061 }, \
00372 { AR5K_AR5210_RF_GAIN(0x07), 0x000000a1 }, \
00373 { AR5K_AR5210_RF_GAIN(0x08), 0x000000e1 }, \
00374 { AR5K_AR5210_RF_GAIN(0x09), 0x00000031 }, \
00375 { AR5K_AR5210_RF_GAIN(0x0a), 0x00000071 }, \
00376 { AR5K_AR5210_RF_GAIN(0x0b), 0x000000b1 }, \
00377 { AR5K_AR5210_RF_GAIN(0x0c), 0x0000001c }, \
00378 { AR5K_AR5210_RF_GAIN(0x0d), 0x0000005c }, \
00379 { AR5K_AR5210_RF_GAIN(0x0e), 0x00000029 }, \
00380 { AR5K_AR5210_RF_GAIN(0x0f), 0x00000069 }, \
00381 { AR5K_AR5210_RF_GAIN(0x10), 0x000000a9 }, \
00382 { AR5K_AR5210_RF_GAIN(0x11), 0x00000020 }, \
00383 { AR5K_AR5210_RF_GAIN(0x12), 0x00000019 }, \
00384 { AR5K_AR5210_RF_GAIN(0x13), 0x00000059 }, \
00385 { AR5K_AR5210_RF_GAIN(0x14), 0x00000099 }, \
00386 { AR5K_AR5210_RF_GAIN(0x15), 0x00000030 }, \
00387 { AR5K_AR5210_RF_GAIN(0x16), 0x00000005 }, \
00388 { AR5K_AR5210_RF_GAIN(0x17), 0x00000025 }, \
00389 { AR5K_AR5210_RF_GAIN(0x18), 0x00000065 }, \
00390 { AR5K_AR5210_RF_GAIN(0x19), 0x000000a5 }, \
00391 { AR5K_AR5210_RF_GAIN(0x1a), 0x00000028 }, \
00392 { AR5K_AR5210_RF_GAIN(0x1b), 0x00000068 }, \
00393 { AR5K_AR5210_RF_GAIN(0x1c), 0x0000001f }, \
00394 { AR5K_AR5210_RF_GAIN(0x1d), 0x0000001e }, \
00395 { AR5K_AR5210_RF_GAIN(0x1e), 0x00000018 }, \
00396 { AR5K_AR5210_RF_GAIN(0x1f), 0x00000058 }, \
00397 { AR5K_AR5210_RF_GAIN(0x20), 0x00000098 }, \
00398 { AR5K_AR5210_RF_GAIN(0x21), 0x00000003 }, \
00399 { AR5K_AR5210_RF_GAIN(0x22), 0x00000004 }, \
00400 { AR5K_AR5210_RF_GAIN(0x23), 0x00000044 }, \
00401 { AR5K_AR5210_RF_GAIN(0x24), 0x00000084 }, \
00402 { AR5K_AR5210_RF_GAIN(0x25), 0x00000013 }, \
00403 { AR5K_AR5210_RF_GAIN(0x26), 0x00000012 }, \
00404 { AR5K_AR5210_RF_GAIN(0x27), 0x00000052 }, \
00405 { AR5K_AR5210_RF_GAIN(0x28), 0x00000092 }, \
00406 { AR5K_AR5210_RF_GAIN(0x29), 0x000000d2 }, \
00407 { AR5K_AR5210_RF_GAIN(0x2a), 0x0000002b }, \
00408 { AR5K_AR5210_RF_GAIN(0x2b), 0x0000002a }, \
00409 { AR5K_AR5210_RF_GAIN(0x2c), 0x0000006a }, \
00410 { AR5K_AR5210_RF_GAIN(0x2d), 0x000000aa }, \
00411 { AR5K_AR5210_RF_GAIN(0x2e), 0x0000001b }, \
00412 { AR5K_AR5210_RF_GAIN(0x2f), 0x0000001a }, \
00413 { AR5K_AR5210_RF_GAIN(0x30), 0x0000005a }, \
00414 { AR5K_AR5210_RF_GAIN(0x31), 0x0000009a }, \
00415 { AR5K_AR5210_RF_GAIN(0x32), 0x000000da }, \
00416 { AR5K_AR5210_RF_GAIN(0x33), 0x00000006 }, \
00417 { AR5K_AR5210_RF_GAIN(0x34), 0x00000006 }, \
00418 { AR5K_AR5210_RF_GAIN(0x35), 0x00000006 }, \
00419 { AR5K_AR5210_RF_GAIN(0x36), 0x00000006 }, \
00420 { AR5K_AR5210_RF_GAIN(0x37), 0x00000006 }, \
00421 { AR5K_AR5210_RF_GAIN(0x38), 0x00000006 }, \
00422 { AR5K_AR5210_RF_GAIN(0x39), 0x00000006 }, \
00423 { AR5K_AR5210_RF_GAIN(0x3a), 0x00000006 }, \
00424 { AR5K_AR5210_RF_GAIN(0x3b), 0x00000006 }, \
00425 { AR5K_AR5210_RF_GAIN(0x3c), 0x00000006 }, \
00426 { AR5K_AR5210_RF_GAIN(0x3d), 0x00000006 }, \
00427 { AR5K_AR5210_RF_GAIN(0x3e), 0x00000006 }, \
00428 { AR5K_AR5210_RF_GAIN(0x3f), 0x00000006 }, \
00429 \
00430 { AR5K_AR5210_PHY(53), 0x00000020 }, \
00431 { AR5K_AR5210_PHY(51), 0x00000004 }, \
00432 { AR5K_AR5210_PHY(50), 0x00060106 }, \
00433 { AR5K_AR5210_PHY(39), 0x0000006d }, \
00434 { AR5K_AR5210_PHY(48), 0x00000000 }, \
00435 { AR5K_AR5210_PHY(52), 0x00000014 }, \
00436 { AR5K_AR5210_PHY_ACTIVE, AR5K_AR5210_PHY_ENABLE }, \
00437 }
00438
00439 #endif
