00001 #ifndef HOSTAP_WLAN_H
00002 #define HOSTAP_WLAN_H
00003
00004 #include "hostap_config.h"
00005 #ifdef __KERNEL__
00006 #include "hostap_compat.h"
00007 #endif
00008 #include "hostap_crypt.h"
00009 #include "hostap_common.h"
00010
00011 #define MAX_PARM_DEVICES 8
00012 #define PARM_MIN_MAX "1-" __MODULE_STRING(MAX_PARM_DEVICES)
00013 #define DEF_INTS -1, -1, -1, -1, -1, -1, -1
00014 #define GET_INT_PARM(var,idx) var[var[idx] < 0 ? 0 : idx]
00015
00016
00017
00018
00019
00020
00021
00022
00023 #define ETH_P_HOSTAP ETH_P_CONTROL
00024
00025 #ifndef ARPHRD_IEEE80211
00026 #define ARPHRD_IEEE80211 801
00027 #endif
00028 #ifndef ARPHRD_IEEE80211_PRISM
00029 #define ARPHRD_IEEE80211_PRISM 802
00030 #endif
00031
00032
00033
00034 struct linux_wlan_ng_val {
00035 u32 did;
00036 u16 status, len;
00037 u32 data;
00038 } __attribute__ ((packed));
00039
00040 struct linux_wlan_ng_prism_hdr {
00041 u32 msgcode, msglen;
00042 char devname[16];
00043 struct linux_wlan_ng_val hosttime, mactime, channel, rssi, sq, signal,
00044 noise, rate, istx, frmlen;
00045 } __attribute__ ((packed));
00046
00047 struct linux_wlan_ng_cap_hdr {
00048 u32 version;
00049 u32 length;
00050 u64 mactime;
00051 u64 hosttime;
00052 u32 phytype;
00053 u32 channel;
00054 u32 datarate;
00055 u32 antenna;
00056 u32 priority;
00057 u32 ssi_type;
00058 s32 ssi_signal;
00059 s32 ssi_noise;
00060 u32 preamble;
00061 u32 encoding;
00062 } __attribute__ ((packed));
00063
00064 #define LWNG_CAP_DID_BASE (4 | (1 << 6))
00065 #define LWNG_CAPHDR_VERSION 0x80211001
00066
00067 struct hfa384x_rx_frame {
00068
00069 u16 status;
00070 u32 time;
00071 u8 silence;
00072 u8 signal;
00073 u8 rate;
00074 u8 rxflow;
00075 u32 reserved;
00076
00077
00078 u16 frame_control;
00079 u16 duration_id;
00080 u8 addr1[6];
00081 u8 addr2[6];
00082 u8 addr3[6];
00083 u16 seq_ctrl;
00084 u8 addr4[6];
00085 u16 data_len;
00086
00087
00088 u8 dst_addr[6];
00089 u8 src_addr[6];
00090 u16 len;
00091
00092
00093 } __attribute__ ((packed));
00094
00095
00096 struct hfa384x_tx_frame {
00097
00098 u16 status;
00099 u16 reserved1;
00100 u16 reserved2;
00101 u32 sw_support;
00102 u8 retry_count;
00103 u8 tx_rate;
00104 u16 tx_control;
00105
00106
00107 u16 frame_control;
00108 u16 duration_id;
00109 u8 addr1[6];
00110 u8 addr2[6];
00111 u8 addr3[6];
00112 u16 seq_ctrl;
00113 u8 addr4[6];
00114 u16 data_len;
00115
00116
00117 u8 dst_addr[6];
00118 u8 src_addr[6];
00119 u16 len;
00120
00121
00122 } __attribute__ ((packed));
00123
00124
00125 struct hfa384x_rid_hdr
00126 {
00127 u16 len;
00128 u16 rid;
00129 } __attribute__ ((packed));
00130
00131
00132
00133
00134 #define HFA384X_LEVEL_TO_dBm(v) 0x100 + (v) * 100 / 255 - 100
00135
00136
00137
00138 #define HFA384X_RSSI_LEVEL_TO_dBm(v) ((v) - 100)
00139
00140 struct hfa384x_scan_request {
00141 u16 channel_list;
00142 u16 txrate;
00143 } __attribute__ ((packed));
00144
00145 struct hfa384x_hostscan_request {
00146 u16 channel_list;
00147 u16 txrate;
00148 u16 target_ssid_len;
00149 u8 target_ssid[32];
00150 } __attribute__ ((packed));
00151
00152 struct hfa384x_join_request {
00153 u8 bssid[6];
00154 u16 channel;
00155 } __attribute__ ((packed));
00156
00157 struct hfa384x_info_frame {
00158 u16 len;
00159 u16 type;
00160 } __attribute__ ((packed));
00161
00162 struct hfa384x_comm_tallies {
00163 u16 tx_unicast_frames;
00164 u16 tx_multicast_frames;
00165 u16 tx_fragments;
00166 u16 tx_unicast_octets;
00167 u16 tx_multicast_octets;
00168 u16 tx_deferred_transmissions;
00169 u16 tx_single_retry_frames;
00170 u16 tx_multiple_retry_frames;
00171 u16 tx_retry_limit_exceeded;
00172 u16 tx_discards;
00173 u16 rx_unicast_frames;
00174 u16 rx_multicast_frames;
00175 u16 rx_fragments;
00176 u16 rx_unicast_octets;
00177 u16 rx_multicast_octets;
00178 u16 rx_fcs_errors;
00179 u16 rx_discards_no_buffer;
00180 u16 tx_discards_wrong_sa;
00181 u16 rx_discards_wep_undecryptable;
00182 u16 rx_message_in_msg_fragments;
00183 u16 rx_message_in_bad_msg_fragments;
00184 } __attribute__ ((packed));
00185
00186 struct hfa384x_comm_tallies32 {
00187 u32 tx_unicast_frames;
00188 u32 tx_multicast_frames;
00189 u32 tx_fragments;
00190 u32 tx_unicast_octets;
00191 u32 tx_multicast_octets;
00192 u32 tx_deferred_transmissions;
00193 u32 tx_single_retry_frames;
00194 u32 tx_multiple_retry_frames;
00195 u32 tx_retry_limit_exceeded;
00196 u32 tx_discards;
00197 u32 rx_unicast_frames;
00198 u32 rx_multicast_frames;
00199 u32 rx_fragments;
00200 u32 rx_unicast_octets;
00201 u32 rx_multicast_octets;
00202 u32 rx_fcs_errors;
00203 u32 rx_discards_no_buffer;
00204 u32 tx_discards_wrong_sa;
00205 u32 rx_discards_wep_undecryptable;
00206 u32 rx_message_in_msg_fragments;
00207 u32 rx_message_in_bad_msg_fragments;
00208 } __attribute__ ((packed));
00209
00210 struct hfa384x_scan_result_hdr {
00211 u16 reserved;
00212 u16 scan_reason;
00213 #define HFA384X_SCAN_IN_PROGRESS 0
00214 #define HFA384X_SCAN_HOST_INITIATED 1
00215 #define HFA384X_SCAN_FIRMWARE_INITIATED 2
00216 #define HFA384X_SCAN_INQUIRY_FROM_HOST 3
00217 } __attribute__ ((packed));
00218
00219 #define HFA384X_SCAN_MAX_RESULTS 32
00220
00221 struct hfa384x_scan_result {
00222 u16 chid;
00223 u16 anl;
00224 u16 sl;
00225 u8 bssid[6];
00226 u16 beacon_interval;
00227 u16 capability;
00228 u16 ssid_len;
00229 u8 ssid[32];
00230 u8 sup_rates[10];
00231 u16 rate;
00232 } __attribute__ ((packed));
00233
00234 struct hfa384x_hostscan_result {
00235 u16 chid;
00236 u16 anl;
00237 u16 sl;
00238 u8 bssid[6];
00239 u16 beacon_interval;
00240 u16 capability;
00241 u16 ssid_len;
00242 u8 ssid[32];
00243 u8 sup_rates[10];
00244 u16 rate;
00245 u16 atim;
00246 } __attribute__ ((packed));
00247
00248 struct comm_tallies_sums {
00249 unsigned int tx_unicast_frames;
00250 unsigned int tx_multicast_frames;
00251 unsigned int tx_fragments;
00252 unsigned int tx_unicast_octets;
00253 unsigned int tx_multicast_octets;
00254 unsigned int tx_deferred_transmissions;
00255 unsigned int tx_single_retry_frames;
00256 unsigned int tx_multiple_retry_frames;
00257 unsigned int tx_retry_limit_exceeded;
00258 unsigned int tx_discards;
00259 unsigned int rx_unicast_frames;
00260 unsigned int rx_multicast_frames;
00261 unsigned int rx_fragments;
00262 unsigned int rx_unicast_octets;
00263 unsigned int rx_multicast_octets;
00264 unsigned int rx_fcs_errors;
00265 unsigned int rx_discards_no_buffer;
00266 unsigned int tx_discards_wrong_sa;
00267 unsigned int rx_discards_wep_undecryptable;
00268 unsigned int rx_message_in_msg_fragments;
00269 unsigned int rx_message_in_bad_msg_fragments;
00270 };
00271
00272
00273 struct hfa384x_regs {
00274 u16 cmd;
00275 u16 evstat;
00276 u16 offset0;
00277 u16 offset1;
00278 u16 swsupport0;
00279 };
00280
00281
00282 #if defined(PRISM2_PCCARD) || defined(PRISM2_PLX)
00283
00284 #define HFA384X_CMD_OFF 0x00
00285 #define HFA384X_PARAM0_OFF 0x02
00286 #define HFA384X_PARAM1_OFF 0x04
00287 #define HFA384X_PARAM2_OFF 0x06
00288 #define HFA384X_STATUS_OFF 0x08
00289 #define HFA384X_RESP0_OFF 0x0A
00290 #define HFA384X_RESP1_OFF 0x0C
00291 #define HFA384X_RESP2_OFF 0x0E
00292 #define HFA384X_INFOFID_OFF 0x10
00293 #define HFA384X_CONTROL_OFF 0x14
00294 #define HFA384X_SELECT0_OFF 0x18
00295 #define HFA384X_SELECT1_OFF 0x1A
00296 #define HFA384X_OFFSET0_OFF 0x1C
00297 #define HFA384X_OFFSET1_OFF 0x1E
00298 #define HFA384X_RXFID_OFF 0x20
00299 #define HFA384X_ALLOCFID_OFF 0x22
00300 #define HFA384X_TXCOMPLFID_OFF 0x24
00301 #define HFA384X_SWSUPPORT0_OFF 0x28
00302 #define HFA384X_SWSUPPORT1_OFF 0x2A
00303 #define HFA384X_SWSUPPORT2_OFF 0x2C
00304 #define HFA384X_EVSTAT_OFF 0x30
00305 #define HFA384X_INTEN_OFF 0x32
00306 #define HFA384X_EVACK_OFF 0x34
00307 #define HFA384X_DATA0_OFF 0x36
00308 #define HFA384X_DATA1_OFF 0x38
00309 #define HFA384X_AUXPAGE_OFF 0x3A
00310 #define HFA384X_AUXOFFSET_OFF 0x3C
00311 #define HFA384X_AUXDATA_OFF 0x3E
00312 #endif
00313
00314 #ifdef PRISM2_PCI
00315
00316 #define HFA384X_CMD_OFF 0x00
00317 #define HFA384X_PARAM0_OFF 0x04
00318 #define HFA384X_PARAM1_OFF 0x08
00319 #define HFA384X_PARAM2_OFF 0x0C
00320 #define HFA384X_STATUS_OFF 0x10
00321 #define HFA384X_RESP0_OFF 0x14
00322 #define HFA384X_RESP1_OFF 0x18
00323 #define HFA384X_RESP2_OFF 0x1C
00324 #define HFA384X_INFOFID_OFF 0x20
00325 #define HFA384X_CONTROL_OFF 0x28
00326 #define HFA384X_SELECT0_OFF 0x30
00327 #define HFA384X_SELECT1_OFF 0x34
00328 #define HFA384X_OFFSET0_OFF 0x38
00329 #define HFA384X_OFFSET1_OFF 0x3C
00330 #define HFA384X_RXFID_OFF 0x40
00331 #define HFA384X_ALLOCFID_OFF 0x44
00332 #define HFA384X_TXCOMPLFID_OFF 0x48
00333 #define HFA384X_PCICOR_OFF 0x4C
00334 #define HFA384X_SWSUPPORT0_OFF 0x50
00335 #define HFA384X_SWSUPPORT1_OFF 0x54
00336 #define HFA384X_SWSUPPORT2_OFF 0x58
00337 #define HFA384X_PCIHCR_OFF 0x5C
00338 #define HFA384X_EVSTAT_OFF 0x60
00339 #define HFA384X_INTEN_OFF 0x64
00340 #define HFA384X_EVACK_OFF 0x68
00341 #define HFA384X_DATA0_OFF 0x6C
00342 #define HFA384X_DATA1_OFF 0x70
00343 #define HFA384X_AUXPAGE_OFF 0x74
00344 #define HFA384X_AUXOFFSET_OFF 0x78
00345 #define HFA384X_AUXDATA_OFF 0x7C
00346 #define HFA384X_PCI_M0_ADDRH_OFF 0x80
00347 #define HFA384X_PCI_M0_ADDRL_OFF 0x84
00348 #define HFA384X_PCI_M0_LEN_OFF 0x88
00349 #define HFA384X_PCI_M0_CTL_OFF 0x8C
00350 #define HFA384X_PCI_STATUS_OFF 0x98
00351 #define HFA384X_PCI_M1_ADDRH_OFF 0xA0
00352 #define HFA384X_PCI_M1_ADDRL_OFF 0xA4
00353 #define HFA384X_PCI_M1_LEN_OFF 0xA8
00354 #define HFA384X_PCI_M1_CTL_OFF 0xAC
00355
00356
00357
00358 #define HFA384X_PCI_CTL_FROM_BAP (BIT(5) | BIT(1) | BIT(0))
00359 #define HFA384X_PCI_CTL_TO_BAP (BIT(5) | BIT(0))
00360
00361 #endif
00362
00363
00364
00365 #define HFA384X_CMDCODE_INIT 0x00
00366 #define HFA384X_CMDCODE_ENABLE 0x01
00367 #define HFA384X_CMDCODE_DISABLE 0x02
00368 #define HFA384X_CMDCODE_ALLOC 0x0A
00369 #define HFA384X_CMDCODE_TRANSMIT 0x0B
00370 #define HFA384X_CMDCODE_INQUIRE 0x11
00371 #define HFA384X_CMDCODE_ACCESS 0x21
00372 #define HFA384X_CMDCODE_ACCESS_WRITE (0x21 | BIT(8))
00373 #define HFA384X_CMDCODE_DOWNLOAD 0x22
00374 #define HFA384X_CMDCODE_READMIF 0x30
00375 #define HFA384X_CMDCODE_WRITEMIF 0x31
00376 #define HFA384X_CMDCODE_TEST 0x38
00377
00378 #define HFA384X_CMDCODE_MASK 0x3F
00379
00380
00381 #define HFA384X_TEST_CHANGE_CHANNEL 0x08
00382 #define HFA384X_TEST_MONITOR 0x0B
00383 #define HFA384X_TEST_XMIT 0x0E
00384 #define HFA384X_TEST_STOP 0x0F
00385 #define HFA384X_TEST_CFG_BITS 0x15
00386 #define HFA384X_TEST_CFG_BIT_ALC BIT(3)
00387
00388 #define HFA384X_CMD_BUSY BIT(15)
00389
00390 #define HFA384X_CMD_TX_RECLAIM BIT(8)
00391
00392 #define HFA384X_OFFSET_ERR BIT(14)
00393 #define HFA384X_OFFSET_BUSY BIT(15)
00394
00395
00396
00397 #define HFA384X_PROGMODE_DISABLE 0
00398 #define HFA384X_PROGMODE_ENABLE_VOLATILE 1
00399 #define HFA384X_PROGMODE_ENABLE_NON_VOLATILE 2
00400 #define HFA384X_PROGMODE_PROGRAM_NON_VOLATILE 3
00401
00402 #define HFA384X_AUX_MAGIC0 0xfe01
00403 #define HFA384X_AUX_MAGIC1 0xdc23
00404 #define HFA384X_AUX_MAGIC2 0xba45
00405
00406 #define HFA384X_AUX_PORT_DISABLED 0
00407 #define HFA384X_AUX_PORT_DISABLE BIT(14)
00408 #define HFA384X_AUX_PORT_ENABLE BIT(15)
00409 #define HFA384X_AUX_PORT_ENABLED (BIT(14) | BIT(15))
00410 #define HFA384X_AUX_PORT_MASK (BIT(14) | BIT(15))
00411
00412 #define PRISM2_PDA_SIZE 1024
00413
00414
00415
00416 #define HFA384X_EV_TICK BIT(15)
00417 #define HFA384X_EV_WTERR BIT(14)
00418 #define HFA384X_EV_INFDROP BIT(13)
00419 #ifdef PRISM2_PCI
00420 #define HFA384X_EV_PCI_M1 BIT(9)
00421 #define HFA384X_EV_PCI_M0 BIT(8)
00422 #endif
00423 #define HFA384X_EV_INFO BIT(7)
00424 #define HFA384X_EV_DTIM BIT(5)
00425 #define HFA384X_EV_CMD BIT(4)
00426 #define HFA384X_EV_ALLOC BIT(3)
00427 #define HFA384X_EV_TXEXC BIT(2)
00428 #define HFA384X_EV_TX BIT(1)
00429 #define HFA384X_EV_RX BIT(0)
00430
00431
00432
00433 #define HFA384X_INFO_HANDOVERADDR 0xF000
00434 #define HFA384X_INFO_HANDOVERDEAUTHADDR 0xF001
00435 #define HFA384X_INFO_COMMTALLIES 0xF100
00436 #define HFA384X_INFO_SCANRESULTS 0xF101
00437 #define HFA384X_INFO_CHANNELINFORESULTS 0xF102
00438 #define HFA384X_INFO_HOSTSCANRESULTS 0xF103
00439 #define HFA384X_INFO_LINKSTATUS 0xF200
00440 #define HFA384X_INFO_ASSOCSTATUS 0xF201
00441 #define HFA384X_INFO_AUTHREQ 0xF202
00442 #define HFA384X_INFO_PSUSERCNT 0xF203
00443 #define HFA384X_INFO_KEYIDCHANGED 0xF204
00444
00445 enum { HFA384X_LINKSTATUS_CONNECTED = 1,
00446 HFA384X_LINKSTATUS_DISCONNECTED = 2,
00447 HFA384X_LINKSTATUS_AP_CHANGE = 3,
00448 HFA384X_LINKSTATUS_AP_OUT_OF_RANGE = 4,
00449 HFA384X_LINKSTATUS_AP_IN_RANGE = 5,
00450 HFA384X_LINKSTATUS_ASSOC_FAILED = 6 };
00451
00452 enum { HFA384X_PORTTYPE_BSS = 1, HFA384X_PORTTYPE_WDS = 2,
00453 HFA384X_PORTTYPE_PSEUDO_IBSS = 3, HFA384X_PORTTYPE_IBSS = 0,
00454 HFA384X_PORTTYPE_HOSTAP = 6 };
00455
00456 #define HFA384X_RATES_1MBPS BIT(0)
00457 #define HFA384X_RATES_2MBPS BIT(1)
00458 #define HFA384X_RATES_5MBPS BIT(2)
00459 #define HFA384X_RATES_11MBPS BIT(3)
00460
00461 #define HFA384X_ROAMING_FIRMWARE 1
00462 #define HFA384X_ROAMING_HOST 2
00463 #define HFA384X_ROAMING_DISABLED 3
00464
00465 #define HFA384X_WEPFLAGS_PRIVACYINVOKED BIT(0)
00466 #define HFA384X_WEPFLAGS_EXCLUDEUNENCRYPTED BIT(1)
00467 #define HFA384X_WEPFLAGS_HOSTENCRYPT BIT(4)
00468 #define HFA384X_WEPFLAGS_HOSTDECRYPT BIT(7)
00469
00470 #define HFA384X_RX_STATUS_MSGTYPE (BIT(15) | BIT(14) | BIT(13))
00471 #define HFA384X_RX_STATUS_PCF BIT(12)
00472 #define HFA384X_RX_STATUS_MACPORT (BIT(10) | BIT(9) | BIT(8))
00473 #define HFA384X_RX_STATUS_UNDECR BIT(1)
00474 #define HFA384X_RX_STATUS_FCSERR BIT(0)
00475
00476 #define HFA384X_RX_STATUS_GET_MSGTYPE(s) \
00477 (((s) & HFA384X_RX_STATUS_MSGTYPE) >> 13)
00478 #define HFA384X_RX_STATUS_GET_MACPORT(s) \
00479 (((s) & HFA384X_RX_STATUS_MACPORT) >> 8)
00480
00481 enum { HFA384X_RX_MSGTYPE_NORMAL = 0, HFA384X_RX_MSGTYPE_RFC1042 = 1,
00482 HFA384X_RX_MSGTYPE_BRIDGETUNNEL = 2, HFA384X_RX_MSGTYPE_MGMT = 4 };
00483
00484
00485 #define HFA384X_TX_CTRL_ALT_RTRY BIT(5)
00486 #define HFA384X_TX_CTRL_802_11 BIT(3)
00487 #define HFA384X_TX_CTRL_802_3 0
00488 #define HFA384X_TX_CTRL_TX_EX BIT(2)
00489 #define HFA384X_TX_CTRL_TX_OK BIT(1)
00490
00491 #define HFA384X_TX_STATUS_RETRYERR BIT(0)
00492 #define HFA384X_TX_STATUS_AGEDERR BIT(1)
00493 #define HFA384X_TX_STATUS_DISCON BIT(2)
00494 #define HFA384X_TX_STATUS_FORMERR BIT(3)
00495
00496
00497 #define HFA386X_CR_TX_CONFIGURE 0x12
00498 #define HFA386X_CR_RX_CONFIGURE 0x14
00499 #define HFA386X_CR_A_D_TEST_MODES2 0x1A
00500 #define HFA386X_CR_MANUAL_TX_POWER 0x3E
00501
00502
00503 #ifdef __KERNEL__
00504
00505 #define PRISM2_TXFID_COUNT 8
00506 #define PRISM2_DATA_MAXLEN 2304
00507 #define PRISM2_TXFID_LEN (PRISM2_DATA_MAXLEN + sizeof(struct hfa384x_tx_frame))
00508 #define PRISM2_TXFID_EMPTY 0xffff
00509 #define PRISM2_TXFID_RESERVED 0xfffe
00510 #define PRISM2_DUMMY_FID 0xffff
00511 #define MAX_SSID_LEN 32
00512 #define MAX_NAME_LEN 32
00513
00514 #define PRISM2_DUMP_RX_HDR BIT(0)
00515 #define PRISM2_DUMP_TX_HDR BIT(1)
00516 #define PRISM2_DUMP_TXEXC_HDR BIT(2)
00517
00518 struct hostap_tx_callback_info {
00519 u16 idx;
00520 void (*func)(struct sk_buff *, int ok, void *);
00521 void *data;
00522 struct hostap_tx_callback_info *next;
00523 };
00524
00525
00526
00527
00528
00529
00530 #define PRISM2_FRAG_CACHE_LEN 4
00531
00532 struct prism2_frag_entry {
00533 unsigned long first_frag_time;
00534 unsigned int seq;
00535 unsigned int last_frag;
00536 struct sk_buff *skb;
00537 u8 src_addr[ETH_ALEN];
00538 u8 dst_addr[ETH_ALEN];
00539 };
00540
00541
00542 struct prism2_crypt_data {
00543 struct list_head list;
00544 struct hostap_crypto_ops *ops;
00545 void *priv;
00546 atomic_t refcnt;
00547 };
00548
00549 struct hostap_cmd_queue {
00550 struct list_head list;
00551 wait_queue_head_t compl;
00552 volatile enum { CMD_SLEEP, CMD_CALLBACK, CMD_COMPLETED } type;
00553 void (*callback)(struct net_device *dev, void *context, u16 resp0,
00554 u16 res);
00555 void *context;
00556 u16 cmd, param0, param1;
00557 u16 resp0, res;
00558 volatile int issued, issuing;
00559
00560 atomic_t usecnt;
00561 int del_req;
00562 };
00563
00564
00565 #define HOSTAP_HW_NO_DISABLE BIT(0)
00566 #define HOSTAP_HW_ENABLE_CMDCOMPL BIT(1)
00567
00568 typedef struct local_info local_info_t;
00569
00570 struct prism2_helper_functions {
00571
00572
00573 int (*card_present)(local_info_t *local);
00574 void (*cor_sreset)(local_info_t *local);
00575 int (*dev_open)(local_info_t *local);
00576 int (*dev_close)(local_info_t *local);
00577 void (*genesis_reset)(local_info_t *local, int hcr);
00578
00579
00580
00581
00582
00583
00584
00585
00586 int (*cmd)(struct net_device *dev, u16 cmd, u16 param0, u16 *param1,
00587 u16 *resp0);
00588 void (*read_regs)(struct net_device *dev, struct hfa384x_regs *regs);
00589 int (*get_rid)(struct net_device *dev, u16 rid, void *buf, int len,
00590 int exact_len);
00591 int (*set_rid)(struct net_device *dev, u16 rid, void *buf, int len);
00592 int (*hw_enable)(struct net_device *dev, int initial);
00593 int (*hw_config)(struct net_device *dev, int initial);
00594 void (*hw_reset)(struct net_device *dev);
00595 void (*hw_shutdown)(struct net_device *dev, int no_disable);
00596 int (*reset_port)(struct net_device *dev);
00597 int (*tx)(struct sk_buff *skb, struct net_device *dev);
00598 void (*schedule_reset)(local_info_t *local);
00599 #ifdef PRISM2_DOWNLOAD_SUPPORT
00600 int (*download)(local_info_t *local,
00601 struct prism2_download_param *param);
00602 #endif
00603 int (*tx_80211)(struct sk_buff *skb, struct net_device *dev);
00604 };
00605
00606
00607 struct prism2_download_data {
00608 u32 dl_cmd;
00609 u32 start_addr;
00610 u32 num_areas;
00611 struct prism2_download_data_area {
00612 u32 addr;
00613 u32 len;
00614 u8 *data;
00615 } data[0];
00616 };
00617
00618
00619
00620
00621
00622 struct local_info {
00623 struct module *hw_module;
00624 int card_idx;
00625 int dev_enabled;
00626 struct net_device *dev;
00627 struct list_head hostap_interfaces;
00628
00629
00630 rwlock_t iface_lock;
00631
00632
00633 spinlock_t cmdlock, baplock, lock;
00634 struct semaphore rid_bap_sem;
00635 u16 infofid;
00636
00637
00638 spinlock_t txfidlock;
00639 int txfid_len;
00640 u16 txfid[PRISM2_TXFID_COUNT];
00641
00642
00643 u16 intransmitfid[PRISM2_TXFID_COUNT];
00644 int next_txfid;
00645
00646 int next_alloc;
00647
00648
00649
00650 #define HOSTAP_BITS_TRANSMIT 0
00651 #define HOSTAP_BITS_BAP_TASKLET 1
00652 #define HOSTAP_BITS_BAP_TASKLET2 2
00653 long bits;
00654
00655 struct ap_data *ap;
00656
00657 char essid[MAX_SSID_LEN + 1];
00658 char name[MAX_NAME_LEN + 1];
00659 int name_set;
00660 u16 channel_mask;
00661 struct comm_tallies_sums comm_tallies;
00662 struct net_device_stats stats;
00663 struct proc_dir_entry *proc;
00664 int iw_mode;
00665 int pseudo_adhoc;
00666
00667 char bssid[ETH_ALEN];
00668 int channel;
00669 int beacon_int;
00670 int dtim_period;
00671 int disable_on_close;
00672 int mtu;
00673 int frame_dump;
00674 int fw_tx_rate_control;
00675 u16 tx_rate_control;
00676 u16 basic_rates;
00677 int hw_resetting;
00678 int hw_ready;
00679 int hw_reset_tries;
00680 int hw_downloading;
00681 int shutdown;
00682 int pri_only;
00683
00684 enum {
00685 PRISM2_TXPOWER_AUTO = 0, PRISM2_TXPOWER_OFF,
00686 PRISM2_TXPOWER_FIXED, PRISM2_TXPOWER_UNKNOWN
00687 } txpower_type;
00688 int txpower;
00689
00690
00691 struct list_head cmd_queue;
00692
00693
00694
00695 #define HOSTAP_CMD_QUEUE_MAX_LEN 16
00696 int cmd_queue_len;
00697
00698
00699
00700 HOSTAP_QUEUE reset_queue;
00701
00702
00703 int is_promisc;
00704 HOSTAP_QUEUE set_multicast_list_queue;
00705
00706 int wds_max_connections;
00707 int wds_connections;
00708 #define HOSTAP_WDS_BROADCAST_RA BIT(0)
00709 #define HOSTAP_WDS_AP_CLIENT BIT(1)
00710 #define HOSTAP_WDS_STANDARD_FRAME BIT(2)
00711 u32 wds_type;
00712 u16 tx_control;
00713 int manual_retry_count;
00714
00715
00716 #ifdef WIRELESS_EXT
00717 struct iw_statistics wstats;
00718 #if WIRELESS_EXT > 13
00719 unsigned long scan_timestamp;
00720 #endif
00721 #endif
00722 enum {
00723 PRISM2_MONITOR_80211 = 0, PRISM2_MONITOR_PRISM = 1,
00724 PRISM2_MONITOR_CAPHDR = 2
00725 } monitor_type;
00726 int (*saved_eth_header_parse)(struct sk_buff *skb,
00727 unsigned char *haddr);
00728 int monitor_allow_fcserr;
00729
00730 int hostapd;
00731
00732 struct net_device *apdev;
00733 struct net_device_stats apdevstats;
00734
00735 char assoc_ap_addr[ETH_ALEN];
00736 struct net_device *stadev;
00737 struct net_device_stats stadevstats;
00738
00739 struct prism2_crypt_data *crypt;
00740 struct timer_list crypt_deinit_timer;
00741 struct list_head crypt_deinit_list;
00742
00743 #define WEP_KEYS 4
00744 #define WEP_KEY_LEN 13
00745 int open_wep;
00746 int host_encrypt;
00747 int host_decrypt;
00748 int fw_encrypt_ok;
00749
00750 int bcrx_sta_key;
00751
00752
00753 struct prism2_frag_entry frag_cache[PRISM2_FRAG_CACHE_LEN];
00754 unsigned int frag_next_idx;
00755
00756 int ieee_802_1x;
00757
00758 int antsel_tx, antsel_rx;
00759 int rts_threshold;
00760 int fragm_threshold;
00761 int auth_algs;
00762
00763 int enh_sec;
00764 int tallies32;
00765
00766 struct prism2_helper_functions *func;
00767
00768 int bus_master_threshold_tx;
00769 int bus_master_threshold_rx;
00770 u8 *bus_m1_buf;
00771
00772 u8 *pda;
00773 int fw_ap;
00774 #define PRISM2_FW_VER(major, minor, variant) \
00775 (((major) << 16) | ((minor) << 8) | variant)
00776 u32 sta_fw_ver;
00777
00778
00779
00780 HOSTAP_TASKLET bap_tasklet;
00781
00782 HOSTAP_TASKLET info_tasklet;
00783 struct sk_buff_head info_list;
00784
00785
00786 struct hostap_tx_callback_info *tx_callback;
00787
00788
00789 HOSTAP_TASKLET rx_tasklet;
00790 struct sk_buff_head rx_list;
00791
00792 HOSTAP_TASKLET sta_tx_exc_tasklet;
00793 struct sk_buff_head sta_tx_exc_list;
00794
00795 int host_roaming;
00796 unsigned long last_join_time;
00797 struct hfa384x_scan_result *last_scan_results;
00798 int last_scan_results_count;
00799 struct hfa384x_hostscan_result *last_hostscan_results;
00800 int last_hostscan_results_count;
00801 enum { PRISM2_SCAN, PRISM2_HOSTSCAN } last_scan_type;
00802 HOSTAP_QUEUE info_queue;
00803 long pending_info;
00804 #define PRISM2_INFO_PENDING_LINKSTATUS 0
00805 #define PRISM2_INFO_PENDING_SCANRESULTS 1
00806 int prev_link_status;
00807 u8 preferred_ap[6];
00808
00809 #ifdef PRISM2_CALLBACK
00810 void *callback_data;
00811
00812
00813 #endif
00814
00815 wait_queue_head_t hostscan_wq;
00816
00817
00818 struct timer_list passive_scan_timer;
00819 int passive_scan_interval;
00820 int passive_scan_channel;
00821 enum { PASSIVE_SCAN_WAIT, PASSIVE_SCAN_LISTEN } passive_scan_state;
00822
00823 struct timer_list tick_timer;
00824 unsigned long last_tick_timer;
00825 unsigned int sw_tick_stuck;
00826
00827 #ifdef PRISM2_DOWNLOAD_SUPPORT
00828
00829 struct prism2_download_data *dl_pri;
00830 struct prism2_download_data *dl_sec;
00831 #endif
00832
00833 #ifdef PRISM2_IO_DEBUG
00834 #define PRISM2_IO_DEBUG_SIZE 10000
00835 u32 io_debug[PRISM2_IO_DEBUG_SIZE];
00836 int io_debug_head;
00837 int io_debug_enabled;
00838 #endif
00839
00840
00841
00842
00843
00844 #ifdef PRISM2_PCCARD
00845 dev_node_t node;
00846 dev_link_t *link;
00847 #endif
00848
00849 #ifdef PRISM2_PLX
00850 unsigned long attr_mem;
00851 unsigned int cor_offset;
00852 #endif
00853
00854 #ifdef PRISM2_PCI
00855 #ifdef PRISM2_BUS_MASTER
00856
00857 int bus_m0_tx_idx;
00858 u8 *bus_m0_buf;
00859
00860
00861 struct sk_buff *rx_skb;
00862 #endif
00863 #ifdef CONFIG_PM
00864 u32 pci_save_state[16];
00865 #endif
00866 #endif
00867
00868
00869
00870 };
00871
00872
00873
00874
00875
00876 struct hostap_interface {
00877 struct list_head list;
00878 struct net_device *dev;
00879 struct local_info *local;
00880 struct net_device_stats stats;
00881 #if WIRELESS_EXT > 15
00882
00883
00884
00885
00886
00887 struct iw_spy_data spy_data;
00888 #endif
00889
00890 enum {
00891 HOSTAP_INTERFACE_MAIN,
00892 HOSTAP_INTERFACE_AP,
00893 HOSTAP_INTERFACE_STA,
00894 HOSTAP_INTERFACE_WDS,
00895 } type;
00896
00897 union {
00898 struct hostap_interface_wds {
00899 u8 remote_addr[ETH_ALEN];
00900 } wds;
00901 } u;
00902
00903 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0))
00904
00905
00906
00907 char name[IFNAMSIZ];
00908 #endif
00909 };
00910
00911
00912 #ifndef PRISM2_NO_DEBUG
00913
00914 #define DEBUG_FID BIT(0)
00915 #define DEBUG_PS BIT(1)
00916 #define DEBUG_FLOW BIT(2)
00917 #define DEBUG_AP BIT(3)
00918 #define DEBUG_HW BIT(4)
00919 #define DEBUG_EXTRA BIT(5)
00920 #define DEBUG_EXTRA2 BIT(6)
00921 #define DEBUG_PS2 BIT(7)
00922 #define DEBUG_MASK (DEBUG_PS | DEBUG_AP | DEBUG_HW | DEBUG_EXTRA)
00923 #define PDEBUG(n, args...) \
00924 do { if ((n) & DEBUG_MASK) printk(KERN_DEBUG args); } while (0)
00925 #define PDEBUG2(n, args...) \
00926 do { if ((n) & DEBUG_MASK) printk(args); } while (0)
00927
00928 #else
00929
00930 #define PDEBUG(n, args...)
00931 #define PDEBUG2(n, args...)
00932
00933 #endif
00934
00935 enum { BAP0 = 0, BAP1 = 1 };
00936
00937 #define PRISM2_IO_DEBUG_CMD_INB 0
00938 #define PRISM2_IO_DEBUG_CMD_INW 1
00939 #define PRISM2_IO_DEBUG_CMD_INSW 2
00940 #define PRISM2_IO_DEBUG_CMD_OUTB 3
00941 #define PRISM2_IO_DEBUG_CMD_OUTW 4
00942 #define PRISM2_IO_DEBUG_CMD_OUTSW 5
00943 #define PRISM2_IO_DEBUG_CMD_ERROR 6
00944 #define PRISM2_IO_DEBUG_CMD_INTERRUPT 7
00945
00946 #ifdef PRISM2_IO_DEBUG
00947
00948 #define PRISM2_IO_DEBUG_ENTRY(cmd, reg, value) \
00949 (((cmd) << 24) | ((reg) << 16) | value)
00950
00951 static inline void prism2_io_debug_add(struct net_device *dev, int cmd,
00952 int reg, int value)
00953 {
00954 local_info_t *local = dev->priv;
00955
00956 if (!local->io_debug_enabled)
00957 return;
00958
00959 local->io_debug[local->io_debug_head] = jiffies & 0xffffffff;
00960 if (++local->io_debug_head >= PRISM2_IO_DEBUG_SIZE)
00961 local->io_debug_head = 0;
00962 local->io_debug[local->io_debug_head] =
00963 PRISM2_IO_DEBUG_ENTRY(cmd, reg, value);
00964 if (++local->io_debug_head >= PRISM2_IO_DEBUG_SIZE)
00965 local->io_debug_head = 0;
00966 }
00967
00968
00969 static inline void prism2_io_debug_error(struct net_device *dev, int err)
00970 {
00971 local_info_t *local = dev->priv;
00972 unsigned long flags;
00973
00974 if (!local->io_debug_enabled)
00975 return;
00976
00977 spin_lock_irqsave(&local->lock, flags);
00978 prism2_io_debug_add(dev, PRISM2_IO_DEBUG_CMD_ERROR, 0, err);
00979 if (local->io_debug_enabled == 1) {
00980 local->io_debug_enabled = 0;
00981 printk(KERN_DEBUG "%s: I/O debug stopped\n", dev->name);
00982 }
00983 spin_unlock_irqrestore(&local->lock, flags);
00984 }
00985
00986 #else
00987
00988 static inline void prism2_io_debug_add(struct net_device *dev, int cmd,
00989 int reg, int value)
00990 {
00991 }
00992
00993 static inline void prism2_io_debug_error(struct net_device *dev, int err)
00994 {
00995 }
00996
00997 #endif
00998
00999
01000 #ifdef PRISM2_CALLBACK
01001 enum {
01002
01003 PRISM2_CALLBACK_ENABLE,
01004
01005
01006 PRISM2_CALLBACK_DISABLE,
01007
01008
01009 PRISM2_CALLBACK_RX_START, PRISM2_CALLBACK_RX_END,
01010 PRISM2_CALLBACK_TX_START, PRISM2_CALLBACK_TX_END
01011 };
01012 void prism2_callback(local_info_t *local, int event);
01013 #else
01014 #define prism2_callback(d, e) do { } while (0)
01015 #endif
01016
01017 #endif
01018
01019 #endif